ADC1115S125 Datasheet, PDF (28/35 Pages) NXP Semiconductors – Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 24. Output clock register (address 0012h) bit description
Bit
Symbol
Access Value Description
7 to 4 -
0000 not used
3
DAVINV
R/W
output clock data valid (DAV) polarity
0
normal
1
inverted
2 to 0 DAVPHASE[2:0]
R/W
DAV phase select
000
output clock shifted (ahead) by 3 ns
001
output clock shifted (ahead) by 2.5 ns
010
output clock shifted (ahead) by 2 ns
011
output clock shifted (ahead) by 1.5 ns
100
output clock shifted (ahead) by 1 ns
101
output clock shifted (ahead) by 0.5 ns
110
default value as defined in timing section
111
output clock shifted (delayed) by 0.5 ns
Table 25. Offset register (address 0013h) bit description
Bit
Symbol
Access Value
Description
7 to 6 -
00
not used
5 to 0 DIG_OFFSET[5:0]
R/W
digital offset adjustment
011111
+31 LSB
...
...
000000 0
...
...
100000
−32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Bit
Symbol
Access Value Description
7 to 3 -
00000 not used
2 to 0 TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
off
001
mid scale
010
−FS
011
+FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern
110
‘1010..1010.’
111
‘010..1010’
Table 27. Test pattern register 2 (address 0015h) bit description
Bit
Symbol
Access Value
Description
7 to 0 TESTPAT_USER[10:3] R/W
00000000 custom digital test pattern (bits 10 to 3)
ADC1115S125_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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