ADC1115S125 Datasheet, PDF (25/35 Pages) NXP Semiconductors – Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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11.6.3 Register allocation map
Table 18. Register allocation map
Addr.
Hex
Register name R/W Bit definition
Bit 7
Bit 6 Bit 5
Bit 4
0005
Reset and
R/W
operating mode
SW_RST
RESERVED[2:0]
0006 Clock
R/W
-
-
-
SE_SEL
Bit 3
-
DIFF_SE
Bit 2
-
-
Bit 1
Bit 0
OP_MODE[1:0]
CLKDIV DCS_EN
0008 Internal reference R/W
-
-
-
-
INTREF_EN
INTREF[2:0]
0010 Input buffer
R/W
-
-
-
-
-
-
IB_IBIAS[1:0
-
]
0011
Output data
R/W
-
-
-
LVDS_
OUTBUF
OUTBUS_SWAP DATA_FORMAT[1:0]
standard.
CMOS
0012 Output clock
R/W
-
-
-
-
DAVINV
DAVPHASE[2:0]
0013 Offset
R/W
-
-
DIG_OFFSET[5:0]
0014
Test pattern 1
R/W
-
-
-
-
-
TESTPAT_SEL[2:0]
0015
Test pattern 2
R/W
TESTPAT_USER[10:3]
0016
Test pattern 3
R/W
TESTPAT_USER[2:0]
-
-
-
-
-
0017 Fast OTR
R/W
-
-
-
-
FASTOTR
FASTOTR_DET[2:0]
0020
CMOS output
R/W
-
-
-
-
DAV_DRV[1:0]
DATA_DRV[1:0]
0021 LVDS DDR O/P 1 R/W
-
- DAVI_x2_EN
DAVI[1:0]
DATAI_x2_EN
DATAI[1:0]
0022 LVDS DDR O/P 2 R/W
-
-
-
-
BIT_BYTE_WISE
LVDS_INT_TER[2:0]
Default
Bin
0000
0000
0000
0001
0000
0000
0000
0011
0000
0000
0000
1110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1110
0000
0000
0000
0000