UM10601 Datasheet, PDF (29/313 Pages) NXP Semiconductors – LPC800 User manual

UM10601 NXP
Semiconductors
Table
Bit
7:0
23_{DS. yIVmU80bSFoA0lR)} Tbi_DDvgftr_{aeeedalnnusceeoce}ts_ri_mrcoa+iprtn_{i1onitpa.rai.oltAtio}gno_lwren_oan_fye_str_ha^C_set_eo^h_ftrr^a_atod^p_ci_t^t₀v_i^e_oxi_nd^r_Fae_F⁴_lr^:_dtv_o^L_iva^P_uil_du_s^C_ee_er⁸_.r_w⁰_De_i⁰g_tIhVis^S_tiht_s^ye_e^Ds_er^R_fq^t(_r^eU^A_ua^m_a^F_cA^T_tliR_ot^Dc_oT_n^Ro_tF_a^A_h^Dn_lR^F_e^Rf_b^TG^iA_pa^gDFD_ru^uTR_odI_g^ArV^Da_rr^F,^R_aa^Tta^AD_tmⁱ_ed^DoFR_m^TRd^AnAFr^D_ee^T(FR_d^Ss_TADs^YDFR_Rv0^TRDA0^S_aARx^FD_e^C_l^TFA4^R_suTO0^FA_e^D_e^T0_DtFRNT4_{RDA)ARDFTFDARTRFADTADFRTFRDATADRF}
31:8 -
Reserved
-
4.6.19 USART fractional generator multiplier value register
All USART peripherals share a common clock U_PCLK, which can be adjusted by a
fractional divider:
U_PCLK = UARTCLKDIV/(1 + MULT/DIV).
UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.
The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider
registers in the SYSCON block:
1. The DIV denominator of the fractional divider value is programmed in the
UARTFRGDIV register. See Table 23.
2. The MULT value programmed in this register is the numerator of the fractional divider
value used by the fractional rate generator to create the fractional component to the
baud rate.
See also:
Section 15.3.1 “Configure the USART clock and baud rate”
Section 15.7.1 “Clocking and Baud rates”
Table 24. USART fractional generator multiplier value register (UARTFRGMULT, address
0x4004 80F4) bit description
Bit Symbol Description
Reset
value
7:0 MULT
Numerator of the fractional divider. MULT is equal to the programmed 0
value.
31:8 -
Reserved
-
4.6.20 External trace buffer command register
<tbd>
Table 25. External trace buffer command register (EXTTRACECMD, address 0x4004 80FC)
bit description
Bit Symbol Description
0
START Trace start command <tbd>
Reset
value
0
1
STOP Trace stop command <tbd>
0
31:2 -
Reserved
0
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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