UM10601 Datasheet, PDF (125/313 Pages) NXP Semiconductors – LPC800 User manual

UM10601 N_T5Ba:iX_{4bt l}P_{e 1SS}S_1Ey9e_mT.m_CbSLoi_CRc_{l T2}o_bn_idV000d_xxxiaru_210leuc_cett_io_onr_SSSSDas_{eeeeel ttttso/aaacculnnnretidddpapurtcccitlllooeeecpnaaaeorrrrndaaatorrtrieeoonnlrroeertovvedneegerriossspueeteetddnprduww(tOhho2eenU.nnTaVccnaPooyClUuuucehTnnoDatt0ueepIxnrrR3ttLHeCeisrroTi.sr1Rretc0Lhso:e,euLrnuavPtndeiniCddfgi.re8eDdd0sooc0swon0Snuox.n}^Dt_ta5Dt^R_pe0tAorer0o^F_in0g^T_sCor^D_{4caotRo0munAu5}^D_sfFn4t^R_eihTgt)^A_iiinsDbuf^F_g^TR_{iUrvtAaDadNdFbRlouIeTFADwleseDFRYn.cTRA.Tr=AFDiip}^TFRm_{1tTAD.ioeDFRnTrRDRvA0ARaFD(eSTFl}^AR_suTFADCee^TDFR_{tTTRDA)ARDFTFDARTRFADTADFRTFRDATADRF}
7:6 SETCLR3
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
0
0x0 Set and clear do not depend on any counter.
0x1 Set and clear are reversed when counter L or the unified counter is counting down.
0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
31:8 -
Reserved
-
10.6.13 SCT conflict resolution register
The registers OUTn_SETn (Section 10.6.24) and OUTnCLRn (Section 10.6.25) allow
both setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register resolves this conflict.
To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event bits in both the Set and Clear registers.
Table 120. SCT conflict resolution register (RES, address 0x5000 4058) bit description
Bit Symbol Value Description
1:0 O0RES
Effect of simultaneous set and clear on output 0.
Reset
value
0
0x0 No change.
0x1 Set output (or clear based on the SETCLR0 field).
0x2 Clear output (or set based on the SETCLR0 field).
0x3 Toggle output.
3:2 O1RES
Effect of simultaneous set and clear on output 1.
0
0x0 No change.
0x1 Set output (or clear based on the SETCLR1 field).
0x2 Clear output (or set based on the SETCLR1 field).
0x3 Toggle output.
5:4 O2RES
Effect of simultaneous set and clear on output 2.
0
0x0 No change.
0x1 Set output (or clear based on the SETCLR2 field).
0x2 Clear output n (or set based on the SETCLR2 field).
0x3 Toggle output.
7:6 O3RES
Effect of simultaneous set and clear on output 3.
0
0x0 No change.
0x1 Set output (or clear based on the SETCLR3 field).
0x2 Clear output (or set based on the SETCLR3 field).
0x3 Toggle output.
31:8 -
-
Reserved
-
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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