UM10601 Datasheet, PDF (149/313 Pages) NXP Semiconductors – LPC800 User manual

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12.5.3.1 Disabling the WWDT clock source
If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and can not
be disbled either by software or by hardware when Sleep, Deep-sleep or Power-down
modes are entered. Therefore, the user must ensure that the watchdog oscillator for each
power mode is enabled before setting bit 5 in the MOD register.
In Deep power-down mode, no clock locking mechanism is in effect because no clocks
are running. However, an additional lock bit in the PMU can be set to prevent the part from
even entering Deep power-down mode (see Table 42).
12.5.3.2 Changing the WWDT reload value
If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be
changed only after the counter is below the value of WDWARNINT and WDWINDOW.
The reload overwrite lock mechanism can only be disabled by a reset of any type.
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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