UM10601 Datasheet, PDF (136/313 Pages) NXP Semiconductors – LPC800 User manual

UM10601 NXP Sem1i0c.o7n.9d.3uctCo1o.rnsD(–ufiepgfSoiniutnueopertlupee6wtuc,/eotthouvwlenetenehpvneeuertlteta,hsgccaeoihasrmntnteedhadvrietteicpoeenhenvvtrsceeceonanivnntntedofnroiicetCetcic)oldshc:unuparCrsopoOiftonnetMnhsrtheBea1enMs0cfo:iOonuLlpDlnPoutEwCet.ri8on, 0rgo0orwuaSatDptcyaRuotAitmenFcTbCthhDiaoneRnanADEgtfFiRiVioTgnAnnDguF_TR,orCAaDofFbRnTmTADlReaaDFRLTnRtATcAFDrihiTFnRmeTpADageDFRunisTrRDAtdtARFD(eoSTFARrrTsFADCTDFRTTRDA)ARDFTFDARTRFADTADFRTFRDATADRF
– For a match condition:
Select the match register that contains the match condition for the event to occur.
Enter the number of the selected match register in field MATCHSEL.
If using L and H counters, define whether the event occurs on matching the L or
the H counter in field HEVENT.
– For an SCT input or output level or transition:
Select the input number or the output number that is associated with this event in
fields IOSEL and OUTSEL.
Define how the selected input or output triggers the event (edge or level sensitive)
in field IOCOND.
2. Define what the effect of each event is on the SCT outputs in the OUTn_SET or
OUTn_CLR registers (up to 4 outputs, one register per output):
– For each SCT output, select which events set or clear this output. More than one
event can change the output, and each event can change multiple outputs.
3. Define how each event affects the counter:
– Set the corresponding event bit in the LIMIT register for the event to set an upper
limit for the counter.
When a limit event occurs in unidirectional mode, the counter is cleared to zero
and begins counting up on the next clock edge.
When a limit event occurs in bidirectional mode, the counter begins to count down
from the current value on the next clock edge.
– Set the corresponding event bit in the HALT register for the event to halt the
counter. If the counter is halted, it stops counting and no new events can occur.
The counter operation can only be restored by clearing the HALT_L and/or the
HALT_H bits in the CTRL register.
– Set the corresponding event bit in the STOP register for the event to stop the
counter. If the counter is stopped, it stops counting. However, an event that is
configured as a transition on an input/output can restart the counter.
– Set the corresponding event bit in the START register for the event to restart the
counting. Only events that are defined by an input changing can be used to restart
the counter.
4. Define which events contribute to the SCT interrupt:
– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable
the event to contribute to the SCT interrupt.
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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