ADC1010S Datasheet, PDF (28/36 Pages) NXP Semiconductors – Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1010S series
ADC1010S series; CMOS or LVDS DDR digital outputs
Table 22. Internal reference control register (address 0008h) bit description
Bit
Symbol
Access Value
Description
7 to 4 -
0000
not used
3
INTREF_EN
R/W
programmable internal reference enable
0
disable
1
active
2 to 0 INTREF[2:0]
R/W
programmable internal reference
000
0 dB (FS = 2 V)
001
−1 dB (FS = 1.78 V)
010
−2 dB (FS = 1.59 V)
011
−3 dB (FS = 1.42 V)
100
−4 dB (FS = 1.26 V)
101
−5 dB (FS = 1.12 V)
110
−6 dB (FS = 1 V)
111
reserved
Table 23. Output data standard control register (address 0011h) bit description
Bit
Symbol
Access
Value
Description
7 to 5 -
000
not used
4
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
0
CMOS
1
LVDS DDR
3
OUTBUF
R/W
output buffers enable
0
output enabled
1
output disabled (high Z)
2
OUTBUS_SWAP
R/W
output bus swapping
0
no swapping
1
output bus is swapping (MSB becomes LSB and vice
versa)
1 to 0 DATA_FORMAT[1:0]
R/W
output data format
00
offset binary
01
two’s complement
10
gray code
11
offset binary
ADC1010S_SER_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 April 2010
© NXP B.V. 2010. All rights reserved.
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