ADC1010S Datasheet, PDF (12/36 Pages) NXP Semiconductors – Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1010S series
ADC1010S series; CMOS or LVDS DDR digital outputs
10.3 SPI timings
Table 9.
Symbol
t_w(SCLK)
t_w(SCLKH)
t_w(SCLKL)
t_su
SPI timings characteristics
Parameter
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
t_h
hold time
f_clk(max) maximum clock frequency
Conditions
Min Typ
40 -
16 -
16 -
data to SCLK HIGH 5 -
CS to SCLK HIGH 5 -
data to SCLK HIGH 2 -
CS to SCLK HIGH 2 -
-
-
Max Unit
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
25 MHz
[1] Typical values measured at V_DDA = 3 V, V_DDO = 1.8 V, T_amb = 25 °C and C_L = 5 pF; minimum and maximum
values are across the full temperature range T_amb = −40 °C to +85 °C at V_DDA = 3 V, V_DDO = 1.8 V
t_su
CS
t_su
t_h
t_w(SCLK)
t_w(SCLKL)
t_w(SCLKH)
t_h
SCLK
SDIO
R/W W1 W0 A12
A11
Fig 6. SPI timing
D2
D1
D0
005aaa065
11. Application information
11.1 Device control
The ADC1010S can be controlled via SPI or directly via the I/O pins (PIN control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device will remain in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 7.
ADC1010S_SER_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 April 2010
© NXP B.V. 2010. All rights reserved.
12 of 36