TDA8024 Datasheet, PDF (22/29 Pages) NXP Semiconductors – IC card interface

Philips Semiconductors
IC card interface
Product specification
TDA8024
Notes
1. All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is
specified as a function of V_DD or V_CC it means their actual value at the moment of measurement.
2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18
is not connected in the TDA8024AT
3. To meet these specifications, pin V_CC should be decoupled to CGND using two ceramic multilayer capacitors of low
ESR both with values of 100 nF, or one 100 nF and one 220 nF (see Fig.13).
4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF.
5. Transition time and duty factor definitions are shown in Fig.12; δ = _t--1----t₊--¹---t--₂-
6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1.
7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 µA current source to GND
(PRES to V_DD); the card is considered present if at least one of the inputs PRES or PRES is active.
handbook, full pagewidth
tr
90%
tf
90%
10%
10%
t1
t2
VOH
VOH + VOL
2
VOL
MDB058
Fig.12 Definition of output and input transition times.
13 APPLICATION INFORMATION
Performance can be affected by the layout of the
application. For example, an additional cross-capacitance
of 1 pF between card reader contacts C2 and C3 or C2
and C7 can cause contact C2 to be polluted with high
frequency noise from C3 (or C7). In this case, include a
100 pF capacitor between contacts C2 and CGND.
Application recommendations:
• Ensure there is ample ground area around the TDA8024
and the connector; place the TDA8024 very near to the
connector; decouple the V_DD and V_DDP lines (these lines
are best positioned under the connector)
• The TDA8024 and the microcontroller must use the
same V_DD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V,
CMDVCC, and OFF are referred to V_DD; if pin XTAL1 is
to be driven by an external clock, also refer this pin to
V_DD
• Track C3 should be placed as far as possible from the
other tracks
• The track connecting CGND to C5 should be straight
(the two capacitors on C1 should be connected to this
ground track)
• Avoid ground loops between CGND, PGND and GND
• Decouple V_DDP and V_DD separately; if the two supplies
are the same in the application, then they should be
connected in star on the main track.
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 should be less than
100 ps.
Reference layouts are provided in “Application
note 10141”, available on request.
2004 July 12
22