PSMN4R0-30YL Datasheet, PDF (2/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN4R0-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669
(LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
PSMN4R0-30YL LFPAK
4. Limiting values
Description
Version
Plastic single-ended surface-mounted package (LFPAK); SOT669
4 leads
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
V_DS
V_DGR
V_GS
I_D
I_DM
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
T_j ≥ 25 °C; T_j ≤ 150 °C
T_j ≥ 25 °C; T_j ≤ 150 °C; R_GS = 20 kΩ
V_GS = 10 V; T_mb = 100 °C; see Figure 1
V_GS = 10 V; T_mb = 25 °C; see Figure 1
t_p ≤ 10 µs; pulsed; T_mb = 25 °C; see
Figure 3
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_mb = 25 °C; see Figure 2
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_mb = 25 °C
t_p ≤ 10 µs; pulsed; T_mb = 25 °C
E_DS(AL)S
non-repetitive drain-source
avalanche energy
V_GS = 10 V; T_j(init) = 25 °C; I_D = 99 A;
V_sup ≤ 30 V; R_GS = 50 Ω; unclamped
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
70
A
-
99
A
-
396 A
-
69
W
-55 150 °C
-55 150 °C
-
99
A
-
396 A
-
41
mJ
PSMN4R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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