PSMN4R0-30YL Datasheet, PDF (10/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN4R0-30YL
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
L1
HD
E
A
A2
C
b2
c2
mounting
base
D1
L2
1
2
3
4
e
b
wM A
1/2 e
X
c
E1
b3
b4
A
A1 ^C
detail X
(A ₃)
θ
L
yC
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A
A1 A2 A3
b
b2 b3 b4
c
c2
D ⁽¹⁾
D1⁽¹⁾
max
E⁽¹⁾
E1⁽¹⁾
e
H
L L1 L2 w
y
θ
mm ^{1.20 0.15 1.10} 0.25 ^{0.50 4.41 2.2 0.9 0.25 0.30 4.10} 4.20 ^{5.0 3.3} 1.27 ^{6.2 0.85 1.3 1.3} 0.25 0.1
1.01 0.00 0.95
0.35 3.62 2.0 0.7 0.19 0.24 3.80
4.8 3.1
5.8 0.40 0.8 0.8
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT669
MO-235
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
Fig 18. Package outline SOT669 (LFPAK)
PSMN4R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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