TDA8263HN Datasheet, PDF (14/28 Pages) NXP Semiconductors – Fully integrated satellite tuner

Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Table 25: Minimum voltage tuning threshold for calibration control; bits SELVTL[1:0]
These bits control the voltage threshold for the ACDN comparator. The ACUP and ACDN
comparators sense the LC VCO tuning voltage at pin VT.
SELVTL1 SELVTL0 Decimal Threshold VTL (V) ^{[1] [2]}
0
0
0
0.6
0
1
1
0.5
1
0
2
0.4
1
1
3
0.3
[1] Typical values at nominal process and room temperature.
[2] The recommended value is SELVTL[1:0] = 01 (decimal 1).
Table 26: Baseband bias current control; bits BBIAS[3:0]
This register modifies the baseband bias current through different parts: Output buffer or other
amplifier.
BBIAS[3:0]
Value
Binary value
The allowed value is BBIAS[3:0] = 1101 (decimal 13). The product is
specified only with this value, other settings may lead to different
performance.
11.8 Data transfer in read mode
The data transfer in read mode use the following pattern.
Table 27: I²C-bus read mode data transfer pattern
START address
ack data 1
ack
data 2
ack STOP
11.9 I²C-bus table in read mode
Table 28: I²C-bus read mode map ^[1]
Byte MSB
7
6
5
0
POR
LOCK
ACUP
1
1
INLEVEL1 INLEVEL0
4
ACDN
DW4
3
2
ERRORCAL X
DW3
DW2
[1] X can be 1 or 0 and needs to be masked in the microcontrollers’ software; MSB is transmitted first.
1
X
DW1
LSB
0
X
DW0
11.10 Bit description I²C-bus read mode
Table 29: Power-on reset; bit POR
POR
Action
0
Normal operation
1
This bit is set to logic 1 at the V_CC(DIG) power supply ramp-up. It is reset to logic 0
after the first read of the IC.
When V_CC(DIG) falls below 2 V typical, this bit is set to logic 1. This is to prevent loss
in internal I²C-bus registers programming.
9397 750 13193
Product data sheet
Rev. 01 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
14 of 28