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M58WR016QT Datasheet, PDF (89/110 Pages) Numonyx B.V – 16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Common Flash Interface
Table 41. Bank and erase block region 1 information(1)
TOP DEVICES
BOTTOM DEVICES
Offset
Data
Offset
Data
Description
03h(2)
(P+1A)h = 53h
(P+1A)h = 53h 01h
07h(3)
Number of identical banks within Bank Region 1
(P+1B)h = 54h 00h (P+1B)h = 54h 00h
Number of program or erase operations allowed in
Bank region 1:
(P+1C)h = 55h 11h (P+1C)h = 55h 11h Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in
other banks while a bank in same region is
programming
(P+1D)h = 56h 00h (P+1D)h = 56h 00h Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
(P+1E)h = 57h 00h (P+1E)h = 57h 00h Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank region 1
n = number of erase block regions with contiguous
(P+1F)h = 58h 01h (P+1F)h = 58h 02h same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(4)
(P+20)h = 59h 07h (P+20)h = 59h 07h Bank Region 1 Erase Block Type 1 Information
(P+21)h = 5Ah 00h (P+21)h = 5Ah 00h Bits 0-15: n+1 = number of identical-sized erase
blocks in each bank
(P+22)h = 5Bh 00h (P+22)h = 5Bh 20h Bits 16-31: n×256 = number of bytes in erase block
(P+23)h = 5Ch 01h (P+23)h = 5Ch 00h region
(P+24)h = 5Dh 64h (P+24)h = 5Dh 64h Bank Region 1 (Erase Block Type 1)
(P+25)h = 5Eh 00h (P+25)h = 5Eh 00h Minimum block erase cycles × 1000
Bank Region 1 (Erase Block Type 1): BIts per cell,
internal ECC
(P+26)h = 5Fh 01h (P+26)h = 5Fh 01h Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved 5Eh 01 5Eh 01
Bank Region 1 (Erase Block Type 1): Page mode
and synchronous mode capabilities
Bit 0: Page-mode reads permitted
(P+27)h = 60h 03h (P+27)h = 60h 03h Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
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