M58WR016QT Datasheet, PDF (22/110 Pages) Numonyx B.V – 16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories

Command interface - standard commands
M58WR016QT, M58WR016QB, M58WR032QT,
5.6
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error. The Block Erase command can be issued at any moment, regardless of
whether the block has been programmed or not.
Two Bus Write cycles are required to issue the command.
● The first bus cycle sets up the Erase command.
● The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if Reset turns to V_IL. As data integrity cannot
be guaranteed when the Erase operation is aborted, the block must be erased again.
Once the command is issued the device outputs the Status Register data when any address
within the bank is read. At the end of the operation the bank will remain in Read Status
Register mode until a Read Array, Read CFI Query or Read Electronic Signature command
is issued.
During Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored. Refer to Dual
Operations section for detailed information about simultaneous operations allowed in banks
not being erased. Typical Erase times are given in Table 15: Program/Erase times and
endurance cycles.
See Appendix C, Figure 24: Block Erase flowchart and pseudo code, for a suggested
flowchart for using the Block Erase command.
5.7
22/110
Program command
The memory array can be programmed Word-by-Word. Only one Word in one bank can be
programmed at any one time. If the block is protected, the program operation will abort, the
data in the block will not be changed and the Status Register will output the error.
Two bus write cycles are required to issue the Program Command.
● The first bus cycle sets up the Program command.
● The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
After programming has started, read operations in the bank being programmed output the
Status Register content.
During Program operations the bank being programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend command. Refer to Dual Operations section for detailed information about
simultaneous operations allowed in banks not being programmed. Typical Program times
are given in Table 15: Program/Erase times and endurance cycles.
Programming aborts if Reset goes to V_IL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory location must be reprogrammed.
See Appendix C, Figure 20: Program flowchart and pseudo code, for the flowchart for using
the Program command.