M58WR016QT Datasheet, PDF (14/110 Pages) Numonyx B.V – 16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories

Signal descriptions
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
2
Signal descriptions
See Figure 1: Logic Diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-Amax)
Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2
Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V_ILand Reset is at V_IH the device is in active
mode. When Chip Enable is at V_IH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable
whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V_IL, the Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at V_IH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 14: Lock status).
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