M58LR128KC Datasheet, PDF (40/108 Pages) Numonyx B.V – 128 or 256 Mbit (x16, mux I/O, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories

Configuration Register
M58LRxxxKC, M58LRxxxKD
Table 12. Configuration Register
Bit
Description
Value
Description
CR15
CR14
Read select
Reserved
0
Synchronous read
1
Asynchronous read (default at power-on)
010 2 clock latency⁽¹⁾
011 3 clock latency
100 4 clock latency
CR13-CR11 X latency
101 5 clock latency
110 6 clock latency
111 7 clock latency (default)
Other configurations reserved
CR10
CR9
0
Wait polarity
1
0
Data output configuration
1
WAIT is active Low (default)
WAIT is active High
Data held for one clock cycle
Data held for two clock cycles (default)⁽¹⁾
CR8
Wait configuration
0
WAIT is active during WAIT state (default)
1
WAIT is active one data cycle before WAIT
state⁽¹⁾
CR7
Burst type
CR6
Valid clock edge
CR5-CR4 Reserved
0
Reserved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
CR3
Wrap burst
CR2-CR0 Burst length
0
Wrap
1
No wrap (default)
001 4 words
010 8 words
011 16 words
111 Continuous (default)
1. The combination X latency=2, data held for two clock cycles and Wait active one data cycle before the
WAIT state is not supported.
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