M58LR128KC Datasheet, PDF (1/108 Pages) Numonyx B.V – 128 or 256 Mbit (x16, mux I/O, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories

M58LR128KC, M58LR128KD
M58LR256KC, M58LR256KD
128 or 256 Mbit (x16, mux I/O, multiple bank,
multilevel interface, burst) 1.8 V supply Flash memories
Target Specification
Features
■ Supply voltage
– V_DD = 1.7 V to 2.0 V for program, erase and
read
– V_DDQ = 1.7 V to 2.0 V for I/O buffers
– V_PP = 9 V for fast program
■ Multiplexed address/data
■ Synchronous/asynchronous read
– Synchronous burst read mode:
66 MHz, 86 MHz
– Random access: 70 ns
■ Synchronous burst read suspend
■ Programming time
– 2.5 µs typical word program time using
Buffer Enhanced Factory Program
command
■ Memory organization
– Multiple bank memory array:
8 Mbit banks for the M58LR128KC/D
16 Mbit banks for the M58LR256KC/D
– Parameter blocks (top or bottom location)
■ Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
■ Common Flash interface (CFI)
■ 100 000 program/erase cycles per block
Wafer
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for block lock-down
– Absolute write protection with V_PP = V_SS
■ Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ Electronic signature
– Manufacturer code: 20h
– Top device codes:
M58LR128KC: 882Eh
M58LR256KC: 881Ch
– Bottom device codes
M58LR128KD: 882Fh
M58LR256KD: 881Dh
The M58LRxxxKC/D memories are only available as part of a multichip package.
March 2008
Rev 3
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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