M58WR064HU Datasheet, PDF (23/114 Pages) Numonyx B.V – 64 Mbit (4Mb x16, Mux I/O, Multiple Bank, Burst) 1.8V supply Flash memories

M58WR064HU M58WR064HL
Command interface - Standard commands
5.10
Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-Time-
Programmable (OTP) segment of the Protection Register and the Protection Register Lock.
The segment is programmed 16 bits at a time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
● The first bus cycle sets up the Protection Register Program command.
● The second latches the Address and the Data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 4: Protection Register memory map). Attempting to program a previously protected
Protection Register will result in a Status Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended. Dual operations between the
Parameter B ank and the Protection Register memory space are not allowed (see Table 14:
Dual operation limitations). See Appendix C, Figure 28: Protection Register Program
flowchart and pseudo code, for a flowchart for using the Protection Register Program
command.
5.11
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration
Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read
mode and the valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set Configuration Register command.
● The first cycle writes the setup command and the address corresponding to the
Configuration Register content.
● The second cycle writes the Configuration Register data and the confirm command.
Once the command is issued the memory returns to Read mode.
The values of the Configuration Register must always be presented on ADQ15-ADQ0. CR0
is on ADQ0, CR1 on ADQ1, etc.; the other address bits are ignored.
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