M58WR064HU Datasheet, PDF (14/114 Pages) Numonyx B.V – 64 Mbit (4Mb x16, Mux I/O, Multiple Bank, Burst) 1.8V supply Flash memories

Signal descriptions
M58WR064HU M58WR064HL
2.7
Reset/Power-Down (RP)
The Reset/Power-Down input provides a hardware reset of the memory, and/or power-down
functions, depending on the settings in the Configuration Register. When Reset/Power-
Down is at V_IL, the memory is in reset mode: the outputs are high impedance and the
current consumption is reduced to the Standby Supply Current I_DD3, or to the Reset/Power-
Down Supply Current I_DD2 if the Power-Down function is enabled. Refer to Table 20: DC
Characteristics - Currents, for the value of I_DD2 and I_DD3. After reset all blocks are in the
Locked state and the bits of the Configuration Register are reset except for Power-Down bit
CR5. When Reset/Power-Down is at V_IH, the device is in normal operation. Exiting reset
mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V_RPH (refer to Table 21: DC characteristics - voltages).
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-A21 address bits on its rising edge. The
address latch is transparent when Latch Enable is at V_IL and it is inhibited when Latch
Enable is at V_IH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V_IL. Clock is don't care during asynchronous
read and in write operations.
2.10
2.11
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V_IH or Reset is
at V_IL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is forced deasserted when Output Enable is at V_IH.
Bus Invert (BINV)
Bus invert is an input/output signal used to reduce the amount of power required to switch
the external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each
time the inversion results in a reduced number of pin transitions. Data is inverted when BINV
is at V_IH (i.e. if the data is AAAAh and BINV is at V_IH, AAAAh becomes 5555h). BINV is high
impedance when Chip Enable or Output Enable is at V_IH or when Reset/Power Down is at
V_IL.
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