M29DW641F Datasheet, PDF (14/80 Pages) Numonyx B.V – 64 Mbit (4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory

Signal descriptions
M29DW641F
technique (In-System or Programmer technique). See Table 6: Hardware Protection for
details.
The V_PP/Write Protect pin must not be left floating or unconnected or the device may
become unreliable. A 0.1µF capacitor should be connected between the V_PP/Write Protect
pin and the V_SS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
I_PP.
2.7
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all the blocks previously protected using a High voltage
Block Protection technique (In-System or Programmer technique).
Note that if V_PP/WP is at V_IL, then the four outermost parameter blocks will remain protected
even if RP is at V_ID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V_IL, for at
least t_PLPX.
If RP is asserted during a Program or Erase Operation, the RB pin remains Low (busy), until
the internal Reset Operation is completed, which requires a t_PLYH time (see Figure 18:
Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms). The RB
signal can be monitored by the system microprocessor to determine whether the Reset
Operation is completed or not.
If RP is asserted when no Program or Erase Operation is ongoing, the RB pin remains high,
V_IH. A t_PHEL or t_PHGL delay elapses before the Reset Operation is completed and RP returns
to High, V_IH. After this delay, the memory is ready for Bus Read and Bus Write Operations.
Holding RP at V_ID will temporarily unprotect all the blocks previously protected using a High
voltage Block Protection technique. Program and Erase Operations on all blocks will be
possible. The transition from V_IH to V_ID must be slower than t_PHPHH.
See the Ready/Busy Output section, Table 24: Reset/Block Temporary Unprotect AC
characteristics and Figure 18: Reset/Block Temporary Unprotect during Program/Erase
Operation AC waveforms for more details.
2.8
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase Operation. During Program or Erase Operations
Ready/Busy is Low, V_OL. Ready/Busy is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write Operations cannot begin until
Ready/Busy becomes high-impedance. See Table 24 and Figure 18: Reset/Block
Temporary Unprotect during Program/Erase Operation AC waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
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