LMC6681 Datasheet, PDF (9/24 Pages) National Semiconductor (TI) – Low Voltage, Rail-To-Rail Input and Output CMOS

AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T_J = 25˚C, V⁺ = 3V, V− = 0V, V_CM = V_O = V⁺/2, V_PD = 0.6V and R_L > 1
MΩ. Boldface limits apply at the temperature extremes (Note 16).
LMC6681AI LMC6681BI
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6682AI
LMC6684AI
Limit
LMC6682BI
LMC6684BI
Limit
Units
(Note 6)
(Note 6)
t_ON
Time Delay for
Device to Power ON
(Note 15)
50
200
200
µs
t_OFF
Time Delay for
Device to Power OFF
(Note 15)
0.5
2
2
µs
SR
Slew Rate
(Note 8)
1.2
0.7
0.7
V⁺ = 10V, (Note 10)
0.55
1.2
0.7
0.55
V/µs
0.7
min
0.55
0.55
GBW
Gain-Bandwidth Product
1.2
MHz
φ_m
Phase Margin
50
Deg
G_m
Gain Margin
12
dB
Amp-to-Amp Isolation
V⁺ = 10V (Note 9)
130
dB
e_n
Input-Referred
f = 1 kHz
32
Voltage Noise
V_CM = 0.5V
i_n
Input-Referred
f = 1 kHz
0.5
Current Noise
T.H.D.
Total Harmonic Distortion
f = 1 kHz, A_V = +1
0.01
%
R_L = 10 kΩ, V_O = 2 V_PP
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the electrical characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maxi-
mum allowed junction temperature of 150˚C. Output current in excess of ±30 mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of T_{J (max)}, θ_JA, and T_A. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(max)
− T_A)/θ_JA. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V⁺ = 3V, V_CM = 0.5V. For sourcing and sinking, 0.5V ≤ V_O ≤ 2.5V.
Note 8: V⁺ = 3V. Connected as Voltage Follower with 2V step input, and the output is measured from 15%–85%. Number specified is the slower of the positive or
negative slew rates.
Note 9: Input referred, V⁺ = 10V, and R_L = 100 kΩ connected to 5V. Each amp excited in turn with 1 kHz to produce V_O = 2 V_PP.
Note 10: V⁺ = 10V. Connected as voltage follower with 8V step Input, and output is measured from 15%–85%. Number specified is the slower of the positive or nega-
tive slew rates.
Note 11: Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Note 12: Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
Note 13: CMRR⁺ and CMRR^− are tested, and the number indicated is the lower of the two values. For CMRR⁺, V⁺/2 < V_CM < V⁺ for 1.8V, 2.2V, 3V, 5V, and 10V.
For CMRR^−, 0 < V_CM < V⁺/2 for 3V, 5V and 10V. For 1.8V and 2.2V, 0.25 < V_CM < V⁺ − 0.3.
Note 14: V⁺ = 10V, V_CM = 0.5V. For Sourcing tests, 1V ≤ V_O ≤ 5V. For Sinking tests, 5V ≤ V_O ≤ 9V.
Note 15: The propogation delays are measured using an input waveform of f = 5 Hz, and magnitude of 2.4V. Refer to Section 6.3 and Figures 14, 15 for a detailed
explanation.
Note 16: The V_PD (threshold low and threshold high) limits are guaranteed at room temperature and at temperature extremes. Room temperature limits are produc-
tion tested. Limits at temperature extremes are guaranteed via correlation using temperature regression analysis methods. Refer to Section 6.2 for an overview of
the threshold voltages.
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