LMC6681 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – Low Voltage, Rail-To-Rail Input and Output CMOS

3.0 Low Voltage Operation (Continued)
Figure 6 shows an input voltage exceeding both supplies
with no resulting phase inversion on the output.
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FIGURE 7. Resistive Isolation
of a 350 pF Capacitive Load
Figure 8 displays the pulse response of the LMC6681 circuit
in Figure 7.
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FIGURE 6. An Input Voltage Signal Exceeds
LMC6681/2/4 Power Supply Voltages of
V_S = 1.8V with No Output Phase Inversion
4.0 Capacitive Load Tolerance
The LMC6681/2/4 can typically drive a 100 pF load with V_S
= 10V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration to capacitive load.
Direct capacitive loading reduces the phase margin of
op-amps. The combination of the op-amp’s output imped-
ance and the capacitive load induces phase lag. This results
in either an underdamped pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 7. If there is a resistive
component of the load in parallel to the capacitive compo-
nent, the isolation resistor and the resistive load create a
voltage divider at the output. This introduces a DC error at
the output.
FIGURE 8. Pulse Response of the
LMC6681 Circuit in Figure 7
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Another circuit, shown in Figure 9, is also used to indirectly
drive capacitive loads. This circuit is an improvement to the
circuit shown Figure 7 because it provides DC accuracy as
well as AC stability. R1 and C1 serve to counteract the loss
of phase margin by feeding the high frequency component of
the output signal back to the amplifiers inverting input,
thereby preserving phase margin in the overall feedback
loop. The values of R1 and C1 should be experimentally de-
termined by the system designer for the desired pulse re-
sponse. Increased capacitive drive is possible by increasing
the value of the capacitor in the feedback loop.
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FIGURE 9. The LMC6682 Compensated
to Ensure DC Accuracy and AC Stability
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