DS99R421 Datasheet, PDF (9/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Pin Descriptions
Pin #
Pin Name
I/O/PWR
Description
FPD-LINK LVDS RECEIVER INPUT PINS
28, 30, 32 RxIN[2:0]− LVDS_I
LVDS Receiver inverted Data Inputs (−)
29, 31, 33 RxIN[2:0]+ LVDS_I
LVDS Receiver true Data Inputs (+)
34
RxCLKIN− LVDS_I
LVDS Receiver inverted reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
35
RxCLKIN+ LVDS_I
LVDS Receiver true reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
OVER SAMPLED INPUT PINS
3-1
OS[2:0]
LVCMOS_I Over Sampled Receiver Data Inputs with Schmitt trigger
CONTROL AND CONFIGURATION PINS
4
PWDNB
LVCMOS_I Power Down Bar
PWDNB = H; Device is Enabled and ON
PWDNB = L; Device is in power down mode (Sleep), LVDS Driver D_OUT (+/-) Outputs
are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
15
DEN
LVCMOS_I Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Serializer LVDS Driver D_OUT (+/-)
Outputs are in TRI-STATE, PLL still operational and locked to TCLK.
10
PRE
LVCMOS_I Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R_PRE.
Resistor value determines pre-emphasis level. Recommended value R_PRE ≥ 6 kΩ;
I_max = [48 / R_PRE], R_PREmin = 6 kΩ
See Applications Information section for more details.
18
VODSEL
LVCMOS_I VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (R_T = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (R_T = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger
VOD is required, set this pin HIGH.
See Applications Information section for more details.
36, 24, 21, 9 RESRVD
LVCMOS_I/O Reserved. This pin MUST be tied LOW.
BIST MODE PINS
27
BISTEN
LVCMOS_I Control Pin for BIST Mode Enable (ACTIVE H)
BISTEN = L; Default at Low, Normal Mode
BISTEN = H; BIST mode active
Note: Sequence order for proper function of BIST mode:
1) DS99R421 BISTEN = H.
2) DS99R421 PLL must be locked (10 ms).
3) DS90UR124 PLL must be locked.
4) Select BISTM error reporting mode on DS90UR124.
5) DS90UR124 switch BISTEN from L to H.
LVDS SERIALIZER OUTPUT PINS
14
DOUT+
LVDS_O
Serializer LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D_OUT+ pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
13
DOUT−
LVDS_O
Serializer LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D_OUT- pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
5
V_DDP1
V_DD
Analog Power supply, PLL POWER
6
V_SSP1
GND
Analog Ground, PLL GROUND
9
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