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DS99R421 Datasheet, PDF (1/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter | |||
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December 3, 2007
DS99R421
5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single
Embedded Clock DC-Balanced LVDS Converter
General Description
The DS99R421 converts a FPD-Link input with 4 non-DC
Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-
sampled low speed control bits into a single LVDS DC-bal-
anced serial stream with embedded clock information. This
single serial stream simplifies transferring the 24-bit bus over
a single differential pair of PCB traces and cable by eliminat-
ing the skew problems between the 3 parallel LVDS data
inputs and LVDS clock paths. It saves system cost by nar-
rowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB
layers, cable width, connector size, and pins.
The DS99R421 incorporates a single serialized LVDS signal
on the high-speed I/O. Embedded clock LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the converter
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding is used to support AC-Coupled intercon-
nects.
Features
â 5 MHzâ43 MHz embedded clock & DC-Balanced data
transmission (21 total LVDS data bits plus 3 low speed
LVCMOS data bits)
â User adjustable pre-emphasis driving ability through
external resistor on LVDS outputs and capable to drive up
to 10 meters shielded twisted-pair cable
â Supports AC-coupling data transmission
â 100⦠Integrated termination resistor at LVDS input
â Power-down control
â Available @SPEED BIST to DS90UR124 to validate link
integrity
â All LVCMOS inputs & control pins have internal pulldown
â Schmitt trigger inputs on OS[2:0] to minimize metastable
conditions.
â Outputs Tri-Stated through DEN
â On-chip filters for PLLs
â Power supply range 3.3V ± 10%
â Automotive temperature range â40°C to +105°C
â Greater than 8kV ESD Tolerance
â Meets ISO 10605 ESD and AEC-Q100 compliance
Block Diagram
FIGURE 1. Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 300113
30011301
www.national.com
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