DS99R421 Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

clock. The three over sampled bits are mapped to
DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 =
bit 23. If the OS bits are not required, internal pull-down will
bias the input to a LOW.
COLOR MAPPING
Color mapping is application specific. It is very important to
properly match the Pixel bit to the correct data channel on the
DS90UR124 to properly recover the color and control infor-
mation. See Figure 11. In this example, the G0 color bit is
placed in the RxIN0 channel and is the first bit. The Serializer
in the DS99R421 will place this bit as bit number 6. Thus G0
will be recovered by the DS90UR124 on bit 6. The three over
sampled bits are mapped to DS90UR124 bits as: OS0 = bit
21, OS1 = bit 22, and OS2 = bit 23.
POWERDOWN (SLEEP) MODE
The Powerdown state is a low power sleep mode that the
DS99R421 and DS90UR124 may use to reduce power when
no data is being transferred. The PWDNB on the DS99R421
and RPWDNB on the DS90UR124 are used to set each de-
vice into power down mode, which reduces supply current to
the µA range. The DS99R421 enters powerdown when the
PWDNB pin is driven LOW. In powerdown, the PLL stops and
the outputs go into TRI-STATE, disabling load current and
reducing current supply. To powerup, the DS99R421,
PWDNB must be driven HIGH. When the DS99R421 exits
powerdown, its PLL must lock to RxCLKIN before it is ready
for the initialization state. The system must then allow time for
initialization before data transfer can begin.
SERIAL INTERFACE
The serial link between the DS99R421 and the DS90UR124
is intended for a balanced 100 Ohm interconnect. The link is
expected to be terminated at both ends with 100 Ohms and
AC coupled.
To establish a source termination and the correct levels, a
Driver side termination is required. This is typically located
close to the device pins and is 100 Ohm resistor connected
across the driver outputs.
The AC coupling capacitors should be place close to the 100
Ohm termination resistor at both ends of the interface. For the
high-speed LVDS transmission, small footprint packages
should be used for the AC coupling capacitor. This will help
minimize degradation of signal quality due to package para-
sitics. NPO class 1 or X7R class 2 type capacitors are rec-
ommended. 50 WVDC should be the minimum used for best
system-level ESD performance. The most common used ca-
pacitor value for the interface is 100 nF (0.1 uF) capacitor.
The DS90UR124 input stage is designed for AC-coupling by
providing a built-in AC bias network which sets the internal
V_CM to +1.8V. Therefore multiple termination options are pos-
sible.
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the
RIN± pins (see Figure 12). This provides the signal termina-
tion at the Receiver inputs. Other options may be used to
increase noise tolerance.
Receiver Termination Option 2
For additional EMI tolerance, two 50 Ohm resistors may be
used in place of the single 100 Ohm resistor. A small capacitor
is tied from the center point of the 50 Ohm resistors to ground
(see Figure 14). This provides a high-frequency low-
impedance path for noise suppression. Value is not critical,
4.7nF maybe used with general applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider
network may be connected to the center point. This has the
advantage of a providing a DC low-impedance path for noise
suppression. Use resistor values in the range of 100Ω-1KΩ
for the pullup and pulldown. Ratio the resistor values to bias
the center point at 1.8V. For example (see Figure 15):
V_DD=3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; or
Rpullup=100Ω, Rpulldown=120Ω (strongest). The smaller
values will consume more bias current, but will provide en-
hanced noise suppression.
FPD LINK INTERFACE
The FPD-Link Interface supports a 3 Data + Clock (21 bit)
interface. The interconnect should employ a 100 Ohm differ-
ential pair, as termination is provided internal to the
DS99R421. Note that color mapping is extremely important
to review. Color placement of the bits on the FPD-Link Inter-
face will determine which outputs they will be recovered on.
The DS99R421 is expected to reside on the same board as
the FPD-Link Serializer (e.g. DS90C365A or GUI with Inte-
grated FPD-Link Serializer). The DS99R421 supports a lim-
ited common mode range of 525mV to (VDD – VID/2).
Typically this is wide enough to support short interconnects.
@SPEED-BIST (BUILT IN SELF TEST)
The DS99R421/ DS90UR124 serial link is equipped with a
built-in self-test (BIST) capability to support both system man-
ufacturing and field diagnostics.
BIST mode is intended to check the entire high-speed serial
link at full link-speed, without the use of specialized and ex-
pensive test equipment. This feature provides a simple
method for a system host to perform diagnostic testing of both
DS99R421 and DS90UR124. The BIST function is easily
configured through the 2 control pins (BISTEN and BISTM)
on the DS90UR124 and one control pin (BISTEN) of the
DS99R421. When the BIST mode is activated, the DS99R421
has the ability to transfer an internally generated PRBS data
pattern. This pattern traverses across interconnecting links to
the DS90UR124. The DS90UR124 includes an on-chip
PRBS pattern verification circuit that checks the data pattern
for bit errors and reports any errors on the data output pins
on the DS90UR124.
The @SPEED-BIST feature uses 2 control pins (BISTEN and
BISTM) on the DS90UR124 Deserializer. The BISTEN and
BISTM pins together determine the functions of the BIST
mode. The BISTEN signal (HIGH) activates the test feature
on the DS90UR124. After the BIST mode is enabled on the
DS90UR124, toggle the BISTEN pin HIGH on the DS99R421
for the DS90UR124 Deserializer to start accepting data. An
input clock signal (RxCLKIN) for the DS99R421 must also be
applied during the entire BIST operation. Data on RxIN[2:0]
and OS[2:0] are ignored during operation of the BIST. The
BISTM pin on the DS90UR124 selects the error reporting sta-
tus mode of the BIST function. When BIST is configured in
the error status mode (BISTM = LOW), each of the ROUT
[23:0] outputs of the DS90UR124 will correspond to bit errors
on a cycle-by-cycle basis. The result of bit mismatches are
indicated on the respective parallel inputs on the ROUT[23:0]
data output pins. In the BIST error count accumulator mode
(BISTM = HIGH), an 8-bit counter on ROUT[7:0] is used to
represent the number of errors detected (0 to 255 max). The
successful completion of the BIST test is reported on the
PASS pin on the DS90UR124 Deserializer. The DS90UR124
Deserializer's PLL must first be locked to ensure the PASS
status is valid. The PASS status pin will stay LOW and then
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