DS92LV010AEP Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – Bus LVDS 3.3/5.0V Single Transceiver

Application Information
There are a few common practices which should be implied
when designing PCB for BLVDS signaling. Recommended
practices are:
• Use at least 4 layer PCB board (BLVDS signals, ground,
power and TTL signals).
• Keep drivers and receivers as close to the (BLVDS port
side) connector as possible.
• Bypass each BLVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-layer
ceramic (MLC) surface mount capacitors (0.1 µF, and 0.01
µF in parallel should be used between each V_CC and
ground. The capacitors should be as close as possible to
the V_CC pin.
• Use the termination resistor which best matches the
differential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)
TABLE 1. Functional Table
MODE SELECTED
DRIVER MODE
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
DE
RE
H
H
L
L
L
H
H
L
L = Low state
H = High state
X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Pin Name
DIN
DO±/RI±
R_OUT
RE
DE
GND
V_CC
TABLE 2. Transmitter Mode
INPUTS
DE
DI
H
L
H
H
H
2 > & > 0.8
L
X
OUTPUTS
DO+
DO−
L
H
H
L
X
X
Z
Z
TABLE 3. Receiver Mode
INPUTS
OUTPUT
RE
(RI+)-(RI−)
L
L (< −100 mV)
L
L
H (> +100 mV)
H
L
100 mV > & > −100 mV
X
H
X
Z
Pin #
2
6, 7
3
5
1
4
8
TABLE 4. Device Pin Description
Input/Output
I
I/O
O
I
I
NA
NA
Description
TTL Driver Input
LVDS Driver Outputs/LVDS Receiver Inputs
TTL Receiver Output
Receiver Enable TTL Input (Active Low)
Driver Enable TTL Input (Active High)
Ground
Power Supply
9
201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19
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