DS90CR213 Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link─66 MHz

AC Timing Diagrams (Continued)
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
DS012888-19
DS012888-20
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew—Typically 10 ps–40 ps per foot
FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR213 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
GND
I/O No.
Description
I
21 TTL level inputs.
O
3 Positive LVDS differential data output.
O
3 Negative LVDS differentiaI data output.
I
1 TTL level clock input. The rising edge acts as data strobe.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
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PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv Proof
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