DS90CR213 Datasheet, PDF (5/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link─66 MHz

Receiver Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
RxCLK OUT Period (Figure 7 )
RxCLK OUT High Time (Figure 7 )
f = 40 MHz
f = 66 MHz
RxCLK OUT Low Time (Figure 7 )
f = 40 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 7 )
f = 40 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT (Figure 7 )
f = 40 MHz
f = 66 MHz
RxCLK IN to RxCLK OUT Delay @25˚C, V_CC = 5.0V (Figure 9 )
Receiver Phase Lock Loop Set (Figure 11 )
Receiver Powerdown Delay (Figure 15 )
Min Typ Max Units
15
T
50
ns
6
ns
4.3
5
ns
10.5
ns
7.0
9
ns
4.5
ns
2.5
4.2
ns
6.5
ns
4
5.2
ns
6.4
10.7
ns
10
ms
1
µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
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FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times
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PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv Proof
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