DS90CR213 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link─66 MHz

AC Timing Diagrams (Continued)
FIGURE 12. Seven Bits of LVDS in Once Clock Cycle
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FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR283)
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FIGURE 14. Transmitter Powerdown Delay
FIGURE 15. Receiver Powerdown Delay
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PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv Proof
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