DS3875 Datasheet, PDF (9/58 Pages) National Semiconductor (TI) – Futurebusa┼ Arbitration Controller

3 0 Introduction to DS3875
Arbitration Controller (Continued)
CTRL2
7
6
5
4
3
2
10
F S R U PD5 PD4 PD3 PD2 PDl PD0
During the competition cycle if any module has selected the
slow mode of operation AC0 is asserted during phase 1
for indication to all modules to operate in the slow mode
Thus each arbitration cycle will determine whether the pro-
grammed fast delay value or the programmed slow delay
value is used for the arbitration number settling time delay
The range of values in the fast and slow delay tables are
very close to each other and in some cases are exactly the
same that the desired delay value can be easily chosen
The DS3875 is in complete accordance with 896 1 since
AC0 signal now only is evaluated in phase 3 4 and 5 and
the t_A number is individually determined for each number
Idle Bus Arbitration
Previously the Futurebusa specification allowed idle bus
arbitration Idle Bus Arbitration (IBA) gives a module quick
access to Futurebusa when the current master has com-
pleted it’s transfers IBA occurs on the parallel highway
AD 31 0 lines When the arbitration cycle is in phase 0 and
the master module is not carrying out transactions another
module initiates normal arbitration and IBA simultaneously
In IBA each module is assigned a particular AD 31 0 bit to
assert if a module wishes to get tenure of the bus If more
then one module asserts a bit onto the address data lines
then normal arbitration on the arbitration bus lines will deter-
mine the new master If only one module asserted a bit on
the address data line then during phase 2 of the normal
arbitration cycle that module will be given a bus grant signal
Thus IBA was specified to speed up the arbitration process
when there are not multiple contenders for the bus
IEEE 896 1 no longer allows IBA Now only Parking is al-
lowed It lets the current Futurebusa master quickly access
the bus to perform other transfers when no other modules
want to use it Parking issues the BGRNT signal to the
current bus master during Phase 0
For IEEE 896 1 compliance in the DS3875 the IBA PK bit
of the CTRL3 register should disable IBA and enable Park-
ing On chip reset Parking is selected The IBA CMPT
output signal of the DS3875 should not be connected and
IBA S input signal should be connected to V_CC
Concluding Remarks
In retrospect features which are no longer part of IEEE
896 1 specification were discussed All of these features are
user selectable The DS3875 can be easily configured to
operate in the 896 1 compliance mode As a matter of fact
on power up reset the DS3875 is configured in the compli-
ance mode Briefly
1 Arbitration Number
CTRL2 register R U bit
Unrestricted mode now corresponds with
the 896 1 arbitration number representa-
tion scheme
2 Arbitration Settling Time Delay
CTRL2 register Program as desired
3 IBA
Select a delay from the fast table and
slow table that closely matches the worst
case arbitration settling time number t_A
CTRL3 register IBA PK bit
Enable Parking for 896 1 compliance
which simutanously disables IBA
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