DS3875 Datasheet, PDF (15/58 Pages) National Semiconductor (TI) – Futurebusa┼ Arbitration Controller

5 0 Arbitrating for Futurebus^a (Continued)
5 3 2 Competitor to Send a Message
The Arbitration Controller supports message sending Mes-
sage sending is implemented in the unrestricted mode in a
two pass arbitration cycle The first pass of all ones (1FF H)
in the competition number identifies the transaction as a
message The ALL1 input signal is asserted by the Arbitra-
tion Transceiver when it detects 1FF H on the AB 7 0
and ABp lines The arbitration controller has a hardwired
register that holds the first pass word Further a dedicated
pin MGRQ (message request) places the Arbitration Con-
troller in the message sending mode
The message that is to be transmitted is loaded into the
TXMSG register The message of 1FF H is reserved as the
powerfail message Other messages are to be coded by the
system designer with the greater priority messages having a
higher arbitration number Obviously if more than one mod-
ule simultaneously desires to send a message the message
with the highest arbitration number will be transmitted
When a message is sent no transfer of tenure takes place
Thus the master (M) or the round robin (RR) bits are not
updated Upon successfully transmitting the message
MGTX signal is asserted
When a message is received by the Arbitration Controller
(Phase 5) message interrupt (MGINT ) is asserted and
FIFO Strobe (FSTR ) is negated In the case of a Powerfail
message being received the PFINT signal is asserted
When the PFINT signal is asserted the MGINT and
FSTR signals are not generated See Figure 5d
When sending a message once the MGRQ signal is as-
serted until the message has been transmitted all other
requests are blocked Upon the MGTX signal being re-
leased the message request signal will be reevaluated to
see if another message needs to be sent
If this module is the module sending the arbitration mes-
sage then the message interrupt (MGINT ) or the Powerfail
interrupt (PFINT ) will not be generated on this module
These interrupts are generated only upon the reception of a
message from another module Refer to Figure 5e
5 3 2 1 Using an External FIFO to Store Messages
The Arbitration Controller provides a FIFO strobe (FSTR )
signal to store more than one arbitration message in an
external FIFO A rising edge on FSTR is generated upon
the reception of an arbitration message
See Figure 3 and Timing Diagrams T6 Phase 2 and Phase
5
1 FSTR is always asserted ( FSTR ) during phase 2
2 FSTR is negated (FSTR ) during phase 5 given the fol-
lowing conditions
1 The message is not being sent by this module
2 This is the second pass of an arbitration message
3 No errors occurred during this arbitration cycle
4 This is not a powerfail interrupt message ( PFINT )
The external latch shown in Figure 3 is enabled by AB RE
to temporarily hold the message While AB RE is low
(see timing diagrams phase 2 and 5) the latch is fall
through Then during phase 5 on the rising edge of FSTR
the message held in the latch will be strobed into the FIFO
5 3 3 By-Stander
A Module is considered a by-stander in the arbitration com-
petition if it does not issue a Bus Request ( BRQ ) to the
arbitration controller before arbitration cycle Phase 1 starts
5 3 4 By-Stander Who Decides to Invoke Pre-emption
A module with a higher arbitration number than the master
elect may initiate a new arbitration cycle to establish a new
master This process referred to as pre-emption allows a
high priority to acquire tenure of the bus with minimum laten-
cy
Pre-emption is allowed in phase 3 when all of the following
conditions are met
1 the arbitration number is greater than the arbitration
number on the bus
2 a bus request signal was recently received
3 did not participate in the arbitration competition phase 2
The master elect may be preempted by asserting AC1O
Pre-emption is not allowed during
 the first pass of a two pass cycle
 message sending
These two events are given higher precedence
If a module decides to preempt and changes its competition
number during phase 2 or phase 3 in the Arbitration Control-
ler the Arbitration Transceiver will still use the current
latched competition number to make the greater than com-
parison When the next arbitration cycle occurs the new
competition number will be used
5 3 5 Master
The Master is the module that currently has tenure of the
parallel bus
5 3 6 Master Elect
The Master Elect is the module that won the current arbitra-
tion cycle The Master Elect will become master upon trans-
fer of tenure
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