DS3875 Datasheet, PDF (4/58 Pages) National Semiconductor (TI) – Futurebusa┼ Arbitration Controller

Pin Definition
Pin
of Pins Type
Description
SIGNAL TO FROM THE HANDSHAKE TRANSCEIVER
APO
1
O Arbitration handshake signal from the controller
AQO
1
O Arbitration handshake signal from the controller
ARO
1
O Arbitration handshake signal from the controller
AC0O
1
O Arbitration condition signal from the controller
AC1O
1
O Arbitration condition signal from the controller
API
1
I Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version
of the Futurebusa backplane signal AP
AQI
1
I Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version
of the Futurebusa backplane signal AQ
ARI
1
I Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version
of the Futurebusa backplane signal AR
AC0I
1
I Arbitration condition signal from Futurebusa
AC1I
1
I Arbitration condition signal from Futurebusa
SIGNAL TO FROM THE ARBITRATION TRANSCEIVER (Note These pins are mapped to from the DS3885 Futurebusa
Arbitration Transceiver )
CN(7 0)
8
I O The bus to carry competition number to from the arbitration transceiver
CNp
1
O Parity bit of the competition number
CMPT
1
O Enables the Arbitration number onto Futurebusa
AB RE
1
O Direction control for the competition number bus to from the transceiver
CN LE
1
O Latch enable for latching the Arbitration number from the controller into the transceiver
PER
1
I PARITY ERROR Indicates that a parity error was detected on the winner’s arbitration number
WIN GT
1
I Win signal when competing greater than signal when not competing (used to preempt)
ALL1
1
I Indicates that all the arbitration number lines on the bus are asserted (used for messages)
SIGNALS TO FROM THE PARALLEL PROTOCOL CONTROLLER
BRQ
1
I BUS REQUEST Indicates to the controller to acquire the bus for the module’s use
BGRNT
1
O BUS GRANT Signal asserted by the controller after the detection of a bus request The
module can start using the bus
RINT
1
I Will put the arbitration controller in phase 0 and release all the bus lines except AR A
selective reset is performed The rising edge will release controller from phase 0 This reset is
to be used for bus initialization
RST
1
I Reset signal from the host An internal reset is performed All bus signals are released The
rising edge will put the controller in phase 0 (same as power-up reset)
HALT
1
I Will halt the arbitration controller in phase 0 This signal is for use during live insertion
ENDT
1
I END OF TENURE Indicates the true end of bus tenure of the current master This line may be
asserted only after all the parallel protocol lines are released (Generated via external logic
from BRQ released )
4