DS3875 Datasheet, PDF (38/58 Pages) National Semiconductor (TI) – Futurebusa┼ Arbitration Controller

7 0 Register Description (Continued)
7 11 RXCN1 (ADD(3 0) e 1001)
This register stores the received pass 2 arbitration number of a two pass arbitration number or the single pass arbitration
number (CN7 e 1) in the Unrestricted mode Also this register stores the Restricted Mode arbitration number Defaults to h 80
7
6
5
4
3
2
1
0
1 P1
P0
RR
U4
U3
U2
U1
U0
Bit
Symbol
Description
0–4
U(0 4)
Uniqueness field of the current master master elect
5
RR
Round Robin bit of the current master master elect
6
P0
Priority field of the current master master elect If configured as a two pass arbitor P0 is part of
P(0 7) If configured as a single pass arbitor P0 is the priority field If configured to arbitrate in
restricted mode then P0 is part of P(0 1)
7
1 P1
This field is fixed at one as specified in the spec for the pass 2 number of a two pass arbitration
and for the single pass arbitration number This bit is P1 for the restricted mode arbitration
number of the current master master elect
7 12 RXMSG (ADD(3 0) e 1010)
This register stores the received non-powerfail arbitration message Defaults to h 00
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Bit
Symbol
Description
0–7
A(0 7)
Non-powerfail arbitration message received from another module
7 13 CLRERI (ADD(3 0) e 1011)
Error bits to indicate Parity no BRQ MGRQ or a timeout error A dummy write into this register clears the error interrupt and all
the error bits Defaults to h 00
7
6
5
4
3
2
1
0
ER3
ER2
ER1
Bit
Symbol
Description
7
ER3
Error bit 3 indicates to the winner of the arbitration cycle that BRQ MGRQ signal is no longer
present
6
ER2
Error bit 2 indicates a timeout error
5
ER1
Error bit 1 indicates a Parity error
7 14 CLRMGI (ADD(3 0) e 1100)
7 15 CLRPFI (ADD(3 0) e 1101)
A dummy write into these registers clears the respective interrupt
7
6
5
4
3
2
1
0
Bit
Symbol
0–7
Description
38