PC87306 Datasheet, PDF (88/110 Pages) National Semiconductor (TI) – PC87306 SuperI/OTM Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Pa

10 0 Keyboard Controller and Real-Time Clock (Continued)
where
UIP eUpdate In Progress Bit
UF e Update Ended Flag (Update Ended Interrupt if Enabled)
PF e Periodic Flag (Periodic Interrupt if Enabled)
AF e Alarm Flag (Alarm Interrupt if Enabled)
Flags (and IRQ) are reset at the conclusion of Control Register C read or by RESETC low
A e Update in Progress Bit High before Update Occurs e 244 ms
B e Periodic interrupt to Update e P 2 a 244 ms
C e Update to Alarm Interrupt e 30 5 ms
P e Period is programmed by RS3–0 of control Register A
FIGURE 10-14 Interrupt Status Timing
TL C 12379 – 59
The update occurs 244 ms after the update-in-progress
bit goes high Therefore if a 0 is read there is a minimum
of 244 ms in which the time is guaranteed to remain sta-
ble
Method 4 Use a Periodic interrupt to determine if an
update cycle is in progress
The periodic interrupt is first set to a desired period The
program can then use the periodic interrupt to signify that
there is (Periodic Interrupt 2 a 244 ms) remaining until
another update occurs
The Alarm condition is also generated by the Time Keeping
function After each update the seconds minutes and
hours are compared with the seconds alarm minutes alarm
and hours alarm If equal the Alarm lag is set in Control
Register C This causes an interrupt condition (IRQZ e 0) if
the Alarm Interrupt Enable bit is set in Control Register B If
both bit 7 and bit 6 of any alarm byte (seconds alarm min-
utes alarm hours alarm) are 1 then that alarm byte is a
‘‘don’t care’’
10 2 5 RAM
The RAM data is accessed at locations 0E–7F when
RAMSEL (bit 2) of the configuration registers is 0 and loca-
tions 00 – 7F when RAMSEL is 1 Battery backed power en-
ables the RAM to retain information during system power-
down
Bit 0 of SCF0 locks RTC RAM cells at addresses 38-3Fh
The bit is 0 upon reset thus enabling read and write access
When the bit is 1 writes to RTC RAM cells at addresses
38 – 3Fh are ignored and reads return FFh Once set to 1
the bit can only be cleared by a hardware reset
10 2 6 Power Management
The Power Management function provides power to the
RTC in the PC87306 During system operation power from
the system is used When system voltage falls below battery
voltage the Power Management function switches the RTC
cell to battery power For proper operation a 500 mV differ-
ential is needed between V_CC and V_BAT Figure 10-15 rep-
resents a typical battery configuration and Figure 10-16 rep-
resents typical battery current during battery backed mode
TL C 12379 – 60
FIGURE 10-15 Typical Battery Configuration
TL C 12379 – 61
FIGURE 10-16 Typical Battery Current
during Battery Backed Mode
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