PC87306 Datasheet, PDF (30/110 Pages) National Semiconductor (TI) – PC87306 SuperI/OTM Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Pa

3 0 FDC Register Description (Continued)
D5 Valid Data
Automatic Media Sense mode The state of bit 5
is determined by the state of the VLD0 1 bits in the
ASC Configuration Register If this bit is 0 there is
valid media id sense data in bits 7 and 6 of this
register Bit 5 holds VLD0 when drive 0 is accessed
and media sense is configurfed It holds VLD1 when
drive 1 is accessed and media sense is configured
Otherwise it is set to 1 to indicate that media infor-
mation is not available Valid data should be used
only when accessing drives 0 and 1 See Table 3-4
for details regarding bits 5–7
PC-AT Compatible mode When four drive encod-
ing is used (FER4 e 1) this bit is set to 1
TABLE 3-4 Media ID Bits Functions
Bit 7
Bit 6
Bit 5
Media Type
X
X
1
Invalid Data
0
0
0
5 25
0
1
0
2 88M
1
0
0
1 44M
1
1
0
720k
D4
D3 2
D1 0
Reserved
Bits 3 and 2 are read write bits that control bits con-
trol logical drive exchange
When working with four drives encoding (bit 4 of
FER is 1) the logical drive exchange is not per-
formed
00 No logical drive exchange
01 Logical drive exchange between drives 0 and 1
DR1 internal signal to DR0 pin
MTR1 internal signal to MTR0 pin
DR0 internal signal to DR1 pin
MTR0 internal signal to MTR1 pin
10 Logical drive exchange between drives 0 and 2
The DR0 and MTR0 pins function is exchanged
as follows
DR2 internal signal to DR0 pin
MTR2 internal signal to MTR0 pin
11 Reserved Unpredictable results when 11 is
configured
Tape Select 1 0 These bits assign a logical drive
number to a tape drive Drive 0 is not available as a
tape drive and is reserved as the floppy disk boot
drive See Table 3-5 for the tape drive assignment
values
TABLE 3-5 Tape Drive Assignment Values
TAPESEL1
TAPESEL0
Drive
Selected
0
0
None
0
1
1
1
0
2
1
1
3
3 1 5 Main Status Register (MSR)
Read Only
The read-only Main Status Register indicates the current
status of the disk controller The Main Status Register is
always available to be read One of its functions is to control
the flow of data to and from the Data Register (FIFO) The
Main Status Register indicates when the disk controller is
ready to send or receive data through the Data Register It
should be read before each byte is transferred to or from
the Data Register except during a DMA transfer No delay is
required when reading this register after a data transfer
After a hardware or software reset or recovery from a pow-
er-down state the Main Status Register is immediately
available to be read by the mP It contains a value of 00h
until the oscillator circuit has stabilized and the internal reg-
isters have been initialized When the FDC is ready to re-
ceive a new command it reports an 80h to the mP The
system software can poll the MSR until it is ready The worst
case time allowed for the MSR to report an 80h value (RQM
set) is 2 5 ms after reset or power up
MSR
D7 D6 D5 D4
D3
D2
D1
D0
DESC RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0
DMA PROG BUSY BUSY BUSY BUSY
RESET
0
0
0
0
0
0
0
0
COND
D7 Request for Master Indicates that the controller is
ready to send or receive data from the mP through
the FIFO This bit is cleared immediately after a byte
transfer and is set again as soon as the disk con-
troller is ready for the next byte During a Non-DMA
Execution phase the RQM indicates the status of
the interrupt pin
D6 Data I O (Direction) Indicates whether the con-
troller is expecting a byte to be written to (0) or read
from (1) the Data Register
D5 Non-DMA Execution Indicates that the controller
is in the Execution Phase of a byte transfer opera-
tion in the Non-DMA mode This mode can be used
for multiple byte transfers by the mP in the Execu-
tion Phase via interrupts or software polling
D4 Command in Progress This bit is set after the first
byte of the Command Phase is written This bit is
cleared after the last byte of the Result Phase is
read If there is no Result Phase in a command the
bit is cleared after the last byte of the Command
Phase is written
D3 Drive 3 Busy Set after the last byte of the Com-
mand Phase of a Seek or Recalibrate command is
issued for drive 3 Cleared after reading the first
byte in the Result Phase of the Sense Interrupt
Command for this drive
D2 Drive 2 Busy Same as above but for drive 2
D1 Drive 1 Busy Same as above but for drive 1
D0 Drive 0 Busy Same as above but for drive 0
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