PC87306 Datasheet, PDF (3/110 Pages) National Semiconductor (TI) – PC87306 SuperI/OTM Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Pa

Table of Contents
1 0 PIN DESCRIPTION
2 0 CONFIGURATION REGISTERS
2 1 Overview
2 2 Software Configuration
2 3 Hardware Configuration
2 4 Index and Data Registers
2 5 Base Configuration Registers
2 5 1 Function Enable Register
2 5 2 Function Address Register
2 5 3 Power and Test Register
2 5 4 Function Control Register
2 5 5 Printer Control Register
2 5 6 KBC and RTC Control Register
2 5 7 Power Management Control Register
2 5 8 Tape UARTs and Parallel Port Configuration
Register
2 5 9 SuperI O Identification Register
2 5 10 Advanced SuperI O Configuration Register
2 5 11 Chip Select 0 Low Address
2 5 12 Chip Select 0 High Address
2 5 13 Chip Select 0 Configuration Register
2 5 14 Chip Select 1 Low Address
2 5 15 Chip Select 1 High Address
2 5 16 Chip Select 1 Configuration Register
2 5 17 InfraRed Configuration Register
2 5 18 General Purpose I O Port Base Address
Configuration Register
2 5 19 SuperI O Configuration Register 0
2 5 20 SuperI O Configuration Register 1
2 5 21 LPT Base Address Register
2 5 22 Plug and Play Configuration 0 Register
2 5 23 Plug and Play Configuration 1 Register
2 6 Power-Down Options
2 7 Power-Up Procedure and Considerations
2 7 1 UART Power-Up
2 7 2 FDC Power-Up
3 0 FDC REGISTER DESCRIPTION
3 1 FDC Control Registers
3 1 1 Status Register A (SRA) Read Only
3 1 2 Status Register B (SRB) Read Only
3 1 3 Digital Output Register (DOR) Read Write
3 1 4 Tape Drive Register (TDR) Read Write
3 1 5 Main Status Register (MSR) Read Only
3 1 6 Data Rate Select Register (DSR) Write Only
3 1 7 Data Register (FIFO) Read Write
3 1 8 Digital Input Register (DIR) Read Only
3 1 9 Configuration Control Register (CCR)
Write Only
3 2 Result Phase Status Registers
3 2 1 Status Register 0 (ST0)
3 2 2 Status Register 1 (ST1)
3 0 FDC REGISTER DESCRIPTION (Continued)
3 2 3 Status Register 2 (ST2)
3 2 4 Status Register 3 (ST3)
4 0 FDC COMMAND SET DESCRIPTION
4 1 Command Descriptions
4 1 1 Configure Command
4 1 2 Dumpreg Command
4 1 3 Format Track Command
4 1 4 Invalid Command
4 1 5 Lock Command
4 1 6 Mode Command
4 1 7 NSC Command
4 1 8 Perpendicular Mode Command
4 1 9 Read Data Command
4 1 10 Read Deleted Data Command
4 1 11 Read ID Command
4 1 12 Read A Track Command
4 1 13 Recalibrate Command
4 1 14 Relative Seek Command
4 1 15 Scan Commands
4 1 16 Seek Command
4 1 17 Sense Drive Status Command
4 1 18 Sense Interrupt Command
4 1 19 Set Track Command
4 1 20 Specify Command
4 1 21 Verify Command
4 1 22 Version Command
4 1 23 Write Data Command
4 1 24 Write Deleted Data Command
4 2 Command Set Summary
4 3 Mnemonic Definitions for FDC Commands
5 0 FDC FUNCTIONAL DESCRIPTION
5 1 Microprocessor Interface
5 2 Modes of Operation
5 3 Controller Phases
5 3 1 Command Phase
5 3 2 Execution Phase
5 3 2 1 DMA Mode FIFO Disabled
5 3 2 2 DMA Mode FIFO Enabled
5 3 2 3 Interrupt Mode FIFO Disabled
5 3 2 4 Interrupt Mode FIFO Enabled
5 3 2 5 Software Polling
5 3 3 Result Phase
5 3 4 Idle Phase
5 3 5 Drive Polling Phase
5 4 Data Separator
5 5 Crystal Oscillator
5 6 Perpendicular Recording Mode
5 7 Data Rate Selection
5 8 Write Precompensation
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