PC87306 Datasheet, PDF (75/110 Pages) National Semiconductor (TI) – PC87306 SuperI/OTM Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Pa

8 0 Parallel Port (Continued)
8 6 EXTENDED CAPABILITIES PARALLEL PORT (ECP)
8 6 1 Introduction
The ECP support includes a 16-byte FIFO that can be con-
figured for either direction command data FIFO tags (one
per byte) a FIFO threshold interrupt for both directions
FIFO empty and full status bits automatic generation of
strobes (by hardware) to fill or empty the FIFO transfer of
commands and data and a Run Length Encoding (RLE)
expanding (decompression) as explained below
The Extended Capabilities Port (ECP) is enabled when bit 2
of PCR is 1 Once enabled its mode is controlled via the
mode field of ECR bits 5 6 7 of ECR register
The ECP has ten registers See Table 8-7
The AFIFO CFIFO DFIFO and TFIFO registers access the
same ECP FIFO The FlFO is accessed at Base a 000h or
Base a 400h depending on the mode field of ECR and the
register
FIFO can be accessed by host DMA cycles as well as host
PIO cycles
When DMA is configured and enabled (bit 3 of ECR is 1 and
bit 2 of ECR is 0) the ECP automatically (by hardware) is-
sues DMA requests to fill the FIFO (in the forward direction
when bit 5 of DCR is 0) or to empty the FIFO (in the back-
ward direction when bit 5 of DCR is 1) All DMA transfers are
to or from these registers The ECP does not assert DMA
request for more than 32 consecutive DMA cycles The ECP
stops requesting DMA when TC is detected during an ECP
DMA cycle
Writing into a full FIFO and reading from an empty FIFO
are ignored The written data is lost and the read data is
undefined The FIFO empty and full status bits are not af-
fected by such access
Some registers are not accessible in all modes of operation
or may be accessed in one direction only Accessing a non
accessible register has no effect Data read is undefined
data written is ignored the FIFO does not update The
PV87323VF Parallel Port registers (DRT STR and CTR) are
not accessible when ECP is enabled
To improve noise immunity in ECP cycles the state ma-
chine does not examine the control handshake response
lines until the data has had time to switch
IN ECP mode
DATAR replaces DTR of SPP EPP modes
DSR replaces SPR of SPP EPP modes
DCR replaces CTR of SPP EPP modes
A detailed description of the various modes follows in Sec-
tions 8 8 – 8 11
TABLE 8-7 ECP Registers
Offset
Mode
A10 A1 A0
Register Access Size
Address
ECR (5 – 7)
Function
0 00
0
DATAR
R W Byte 000 001 Parallel Port Data Register
0 00
0
AFIFO
W
Byte
011
ECP Address FIFO
0 01
1
DSR
R
Byte
ALL
Status Register
0 10
2
DCR
R W Byte
ALL
Control Register
1 00
3
CFIFO
W
Byte
010
Parallel Port Data FIFO
1 00
3
DFIFO
R W Byte
011
ECP Data FIFO
1 00
3
TFIFO
R W Byte
110
Test FIFO
1 00
3
CNFGA
R
Byte
111
Configuration Register A
1 01
1 10
4
CNFGB
R
Byte
111
Configuration Register B
5
ECR
R W Byte
ALL
Extended Control Register
The Base address is stored in bits A2–A9 It is 278h 378h or 3BCh as specified in the FAR register
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