DP83843BVJE Datasheet, PDF (80/87 Pages) National Semiconductor (TI) – PHYTER

9.0 Electrical Specifications (Continued)
9.6 Auto-Negotiation Fast Link Pulse (FLP) Timing
T6.21.1
FAST LINK PULSE(S)
T6.21.
T6.21.
T6.21.
1
CLOCK
PULSE
DATA
PULSE
CLOCK
PULSE
T6.21.4
T6.21.5
T6.21.
FLP BURST
Parameter
Description
T6.21.1
Clock, Data Pulse Width
T6.21.2
Clock Pulse to Clock Pulse
Period
T6.21.3
Clock Pulse to Data Pulse
Period
Data = 1
T6.21.4
Number of Pulses in a Burst
T6.21.5
Burst Width
T6.21.6
FLP Burst to FLP Burst Period
Notes
Note: These specifications represent both transmit and receive timings.
9.7 100BASE-X Clock Recovery Module (CRM) Timing
NOMINAL WINDOW
CENTER
FXRD+/-
TPRD+/-
T7.21.1
IDEAL WINDOW RECOGNITION
Parameter
Description
T7.21.1
CRM Window Recognition Region
Note: The Ideal window recognition region is ± 4 ns.
Notes
FLP BURST
Min Typ Max Units
100
ns
111 125 139 µs
55.5
69.5 µs
17
33
#
2
ms
8
24 ms
Min Typ Max Units
-2.7
2.7 ns
80
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