DP83843BVJE Datasheet, PDF (1/87 Pages) National Semiconductor (TI) – PHYTER

July 1999
DP83843BVJE PHYTER
General Description
Features
The DP83843BVJE is a full feature Physical Layer device
with integrated PMD sublayers to support both 10BASE-T
and 100BASE-X Ethernet protocols.
This VLSI device is designed for easy implementation of
10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted
Pair media through an external transformer or to fiber
media via industry standard electrical/optical fiber PMD
transceivers. This device also interfaces directly to the
MAC layer through the IEEE 802.3u standard Media Inde-
pendent Interface (MII), ensuring interoperability between
products from different vendors.
The DP83843 is designed with National Semiconductor's
advanced CMOS process. Its system architecture is based
on the integration of several of National's industry proven
core technologies:
— IEEE 802.3 ENDEC with AUI/10BASE-T transceiver
module to provide the 10 Mb/s functions
— Clock Recovery/Generator Modules from National's Fast
Ethernet and FDDI products
— FDDI Stream Cipher scrambler/descrambler for
TP-PMD
— 100BASE-X physical coding sub-layer (PCS) and control
logic that integrates the core modules into a dual speed
Ethernet physical layer controller
— ANSI X3T12 Compliant TP-PMD Transceiver
technology with Baseline Wander (BLW) compensation
— IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
and built-in filters
— IEEE 802.3u 100BASE-TX compatible - directly drives
standard Category 5 UTP, no need for external
100BASE-TX transceiver
— Fully Integrated and fully compliant ANSI X3.263 TP-
PMD physical sublayer which includes adaptive equal-
ization and BLW compensation
— IEEE 802.3u 100BASE-FX compatible - connects direct-
ly to industry standard Electrical/Optical transceivers
— IEEE 802.3u Auto-Negotiation for automatic speed se-
lection
— IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface
— Integrated high performance 100 Mb/s clock recovery
circuitry requiring no external filters
— Full Duplex support for 10 and 100 Mb/s data rates
— MII Serial 10 Mb/s mode
— Fully configurable node/switch and 100Mb/s repeater
modes
— Programmable loopback modes for flexible system diag-
nostics
— Flexible LED support
— Single register access to complete PHY status
— MDIO interrupt support
— Individualized scrambler seed for 100BASE-TX applica-
tions using multiple PHYs
— Low power consumption for multi-port applications
— Small footprint 80-pin PQFP package
System Diagram
10BASE-T or
100BASE-TX
MII
10 AND/OR 100 Mb/s
ETHERNET MAC OR
100Mb/s REPEATER
CONTROLLER
DP83843
10/100 Mb/s
ETHERNET PHYSICAL LAYER
10BASE-T
RJ-45
or
100BASE-TX
25 MHz
CLOCK
STATUS
LEDS
ThunderLAN^® is a registered trademark of Texas Instruments.
TWISTER™ is a trademark of National Semiconductor Corporation.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
100BASE-FX/
AUI
www.national.com