DP83843BVJE Datasheet, PDF (11/87 Pages) National Semiconductor (TI) – PHYTER

1.0 Pin Descriptions (Continued)
1.6 PHY Address Interface
(00000) will result in a PHY isolation condition as a
The DP83843 PHYAD[4:0] inputs provide up to 32 unique ^{result of power-on/reset, as specified in IEEE 802.3u.}
PHY address options. An address selection of all zeros
Signal Name
PHYAD[0]
(LED_COL)
Type
I/O
PHYAD[1]
I/O
(LED_TX)
PHYAD[2]
I/O
(LED_RX)
PHYAD[3]
I/O
(LED_LINK)
PHYAD[4]
I/O
(LED_FDPOL)
1.7 Reset
Pin #
Description
42
PHY ADDRESS [0]: PHY address sensing pin for multiple PHY applications. PHY
address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10
kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYCTRL register (ad-
dress 19h, bit 0) during power up/reset.
41
PHY ADDRESS [1]: PHY address sensing pin for multiple PHY applications. PHY
address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10
kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYCTRL register (ad-
dress 19h, bit 1) during power up/reset.
40
PHY ADDRESS [2]: PHY address sensing pin for multiple PHY applications. PHY
address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10
kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYCTRL register (ad-
dress 19h, bit 2) during power up/reset.
39
PHY ADDRESS [3]: PHY address sensing pin for multiple PHY applications. PHY
address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10
kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYCTRL register (ad-
dress 19h, bit 3) during power up/reset.
38
PHY ADDRESS [4]: PHY address sensing pin for multiple PHY applications. PHY
address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10
kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYCTRL register (ad-
dress 19h, bit 4) during power up/reset.
Signal Name Type
RESET
I
Pin #
Description
1
RESET: Active high input that initializes or reinitializes the DP83843. Asserting this
pin will force a reset process to occur which will result in all internal registers reini-
tializing to their default states as specified for each bit in section 7.0, and all strap-
ping options are reinitialized. Refer to section 5.0 for further detail regarding reset.
11
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