DP83843BVJE Datasheet, PDF (33/87 Pages) National Semiconductor (TI) – PHYTER

3.0 Configuration (Continued)
3.8 Repeater vs. Node
The DP83843 Carrier Sense (CRS) operation depends on
the value of the Repeater bit in the PHYCTRL register (bit
9, address 19h). When set high, the CRS output (pin 22) is
asserted for receive activity only. When set low, the CRS
output is asserted for either receive or transmit activity. The
default value for this bit is set by the THIN/REPEATER pin
(pin 63) at power-up/reset.
There is an internal pullup resistor for this pin which is
active during the power-up/reset period. If this pin is left
floating externally, then the device will configure to
Repeater mode as a result of power-up/reset. This pin
must be externally pulled low (typically 10 kΩ) in order to
configure the DP83843 for node operation.
When the repeater mode of operation is selected during
100 Mb/s operation, there are two parameters that are
directly effected.
First, CRS will only respond to receive activity.
Second, in compliance with the 802.3 standard, the Carrier
Integrity Monitor (CIM) function is automatically enabled for
detection and reporting of bad start of stream delimiters
(whereas in node mode the CIM is disabled).
diagnostic, this mode serves as quick functional verification
of the device.
In addition to Loopback mode, there are many other test
modes that serve similar loopback functions. These modes
are mutually exclusive with Loopback mode, enabling
Loopback mode disables the following test modes:
— CP_Loop (bits 9:7) of the Loopback and Bypass Register
(LBR). These bits control the 100 Mb/s loopback func-
tions in more depth. A write of either a 0 or 1 to ‘Loop-
back’ causes these bits to be set to <000> which is
normal operation. At reset if FXEN is true then this will
default to, <011> which is Normal Fiber operation, other-
wise it will default to <000>. The other modes are ex-
plained in the LBR definition table.
— Dig_Loop (bit 6) of the LBR. Digital loopback is used to
place the digital portions of the DP83843 into loopback
prior to the signals entering the analog sections. A write
of either a 0 or 1 to ‘Loopback’ causes this bits to be set
to 0 which is digital loopback disabled.
Bit 5 and Bit 4 of the LBR are automatically enabled in
Loopback mode. They are TWISTER (100 Mb/s) loopback
and TREX (10 Mb/s) loopback modes respectively.
The Dp83843 does not support 10Mb/s repeater applica-
tions.
3.9 Isolate Mode
An IEEE 802.3u compliant PHY connected to the mechani-
cal MII interface is required to have a default value of one in
bit 10 of the Basic Mode Control Register (BMCR, address
00h.) The DP83843 will set this bit to one if the PHY
Address is set to 00000 upon power-up/hardware reset.
Otherwise, the DP83843 will set this bit to zero upon
power-up/hardware reset. Refer to Section 2.4.2 for infor-
mation relating to the requirements for selecting a given
PHYAD.
With bit 10 in the BMCR set to one the DP83843 does not
respond to packet data present at TXD[3:0], TX_EN, and
TX_ER inputs and presents a high impedance on the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and
CRS outputs. The DP83843 will continue to respond to all
management transactions.
While in Isolate mode, the TD+/− outputs will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
3.10 Loopback
The DP83843 includes a Loopback Test mode for easy
board diagnostics. The Loopback mode is selected through
bit 14 (‘Loopback’) of the Basic Mode Control Register
(BMCR). The status of this mode may be checked in bit 3
of the PHY Status Register. Writing 1 to this bit enables MII
transmit data to be routed to the MII receive outputs. In
Loopback mode the data will not be transmitted on to the
media. This occurs for either 10 Mb/s or 100 Mb/s data.
Normal 10BASE-T, 10BASE-2, or 10BASE-5 operation, in
order to be standard compliant, also loops back the MII
transmit data to the MII receive data. However the data is
also allowed to be transmitted out the AUI or TP ports
(depending on the mode).
In 100 Mb/s Loopback mode the data is routed through the
PCS and PMA layers into the PMD sublayer before it is
looped back. Therefore, in addition to serving as a board
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