DS92LV8028 Datasheet, PDF (8/16 Pages) National Semiconductor (TI) – 8 Channel 10:1 Serializer

Functional Description
The DS92LV8028 combines eight 10:1 serializers into a
single chip. Each of the eight serializers accepts 10 or less
data bits. The serializers then multiplex the data into a serial
stream with embedded clock bits and route to the LVDS
output. The LVDS output is a 5 mA current loop driver. It
provides enough drive for point-to-point and lightly loaded
multidrop applications. The serialized data stream is com-
patible with the DS92LV1210, DS92LV1212A, DS92LV1224,
DS92LV1260 10-bit deserializers from National Semicon-
ductor.
Each of the eight channels on the DS92LV8028 has their
own serializer function but share a single PLL. There is a
single Transmit Clock (TCLK) for all eight channels. The data
on all eight 10-bit interfaces is latched into the device with
the rising edge of TCLK. Each of the serialized data streams
is independent of the others and includes the embedded
clock information. The skew between the serializer outputs is
minimal.
There is a master power-down signal (MS_PWDN) to put the
entire device into a low power consumption state. In addi-
tion, there is a power-down control signal for each of the
eight channels. This allows the device to efficiently operate
as one to eight 10-bit serializers.
The @SPEED TEST signal initiates the sending of a random
data pattern over the LVDS links. This allows for testing the
links for bit error rates at the frequency they will be carrying
data. In addition, the JTAG boundary scan circuits will be
added to the device at a later date. The JTAG signal pins are
reserved on this version. See package connection diagram.
The DS92LV8028 has four operating modes. They are the
Initialization, Data Transfer, Resynchronization, @SPEED
TEST states. In addition, there are two passive states:
Power-down and TRI-STATE.
The following sections describe each operating mode and
passive state.
Initialization
Before the ’8028 serializes and transmits data, it and the
receiving deserializer device(s) must initialize the link. Initial-
ization refers to synchronizing the Serializer’s and the Dese-
rializer’s PLLs to local clocks. The local clocks should be the
same frequency, or within the specified range if from different
sources. After all devices synchronize to local clocks, the
Deserializers synchronize to the Serializers as the second
and final initialization step.
Step 1: After applying power to the serializer, the outputs are
held in TRI-STATE and the on-chip power-sequencing cir-
cuitry disables the internal circuits. When Vcc reaches
VccOK (2.1V), the PLL in the serializer begins locking to the
local clock (TCLK). A local on-board data source or other
source provides the specified clock input to the TCLK pin.
After locking to TCLK, the serializer is now ready to send
data or SYNC patterns, depending on the level of the SYNC
input or a data stream at the data inputs. The SYNC pattern
sent by the serializer consists of six ones and six zeros
switching at the input clock rate.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. (Refer to the deserializer
data sheet for operation details during this step of the Initial-
ization State.) The Deserializer identifies the rising clock
edge in a synchronization pattern or non-repetitive data
pattern. Depending on the data pattern that it is being trans-
mitted, the Deserializer will synchronize to the data stream
from the Serializer after some delay. At the point where the
Deserializer’s PLL locks to the embedded clock, the LOCK
pin goes low and valid data appears on the output.
The user’s application determines control of the SYNC sig-
nal input. One recommendation is a direct feedback loop
from the LOCK pin on the deserializer. The serializer stops
sending SYNC patterns when the SYNC input returns to a
low state.
Data Transfer
After initialization, the serializer accepts data from the inputs
DINn0 to DINn9. The serializer uses the rising edge of the
TCLK input to latch incoming data. If the SYNCn input is high
for 4 TCLK cycles, the data on DINn0-DINn9 is ignored and
SYNC pulses are transferred.
The serial data stream includes a start bit and stop bit
appended by the serializer, which frame the ten data bits.
The start bit is always high and the stop bit is always low.
The start and stop bits also function as clock bits embedded
in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at
12 times the TCLK frequency. For example, if TCLK is 40
MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10
bits are from input data, the serial ’payload’ rate is 10 times
the TCLK frequency. For instance, if TCLK = 40 MHz, the
payload data rate is 40 X 10 = 400 Mbps. TCLK is provided
by the data source and must be in the range 25 MHz to 66
MHz nominal.
The serializer outputs (DO0± – DO7±) can drive a point-to-
point connection or lightly loaded multidrop connections. The
outputs transmit data when the driver enable pin (DEN) is
high, MS_PWDN and PWDNn are high, and SYNCn is low.
When DEN is driven low, all the serializer output pins will
enter TRI-STATE.
When any one of eight attached Deserializer channels syn-
chronizes to the input from the Serializer, it drives its LOCK
pin low and synchronously delivers valid data on the output.
The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and drives the em-
bedded clock on the RCLK pin. The RCLK is synchronous to
the data on the ROUT pins. While LOCK is low, data on
ROUT is valid. Otherwise, ROUT is invalid.
Resynchronization
Whenever one of the connected DS92LV1212, ’1212A,
’1224, or ’1260 deserializers loses lock, it will automatically
try to resynchronize to the data stream from the serializer. If
the data stream is not a repetitive pattern, then the deseri-
alizer will automatically lock.
For example, if the deserializer’s received embedded clock
edge is not detected two times in succession, the PLL loses
lock and the LOCK pin is driven high. The ’1212, ’1212A,
’1224, or ’1260 deserializers will automatically begin search-
ing for the embedded clock edge. If it is a random data
pattern, the deserializer will lock to that stream. If the data
pattern is repetitive, the deserializer’s PLL will not lock in
order to prevent the deserializer to lock to the data pattern
rather than the clock. We refer to such patterns as repetitive-
multiple-transition, RMT.
Therefore, if the data stream is not random data or the
deserializer is the DS92LV1210, there needs to be a feed-
back path from the deserializer to the serializer. This feed-
back path can be as simple as connecting the deserializer’s
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