DS92LV8028 Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – 8 Channel 10:1 Serializer

Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
R_L = 100Ω
DINn(0-9), TCLK,
t_SD
Serializer Delay
C_L=10pF to GND
DOn+, DOn-
t_TCP + 3.2
t_TCP + 3.5
Figure 7
t_ICR
t_MCR
Individual Channel
Power up Time
Master Power up
Time
R_L = 100Ω,
C_L=10pF to GND
TCLK, DOn+,
DOn-, PWDNn
TCLK, DOn+,
DOn-, MS_PWDN
Figure 6
60*t_TCP
510*t_TCP
63*t_TCP
@Speed Test Enable
t_STE
Time
@Speed Test Disable
t_STD
Time
R_L = 100Ω
R_L = 100Ω
BIST_ACT,
BIST_SEL (0:3),
TCLK, DOn+,
DOn-
10*t_TCP
7*t_TCP
t_SKEW
t_RJIT
Channel to Channel
Skew
Random Jitter
R_L = 100Ω,
C_L=10pF to GND
R_L = 100Ω,
C_L=10pF to GND
(Note 5)
(Note 6)
25 MHz
66 MHz
25MHz
66MHz
130
80
18.4
7.5
R_L = 100Ω,
25MHz
−130
−45
t_DJIT
Deterministic Jitter, C_L=10pF to GND
Figure 9
(Note 5)
66MHz
−190
−92
(Note 7)
Max
Units
t_TCP + 6
ns
70*t_TCP
ns
513*t_TCP
ns
ns
ns
ps
ps
20.7
ps
8.8
ps
40
ps
−40
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, and ∆VOD
which are differential voltages.
Note 4: BIST_SEL pins are pull-up internally.
Note 5: t_LLHT, t_LHLT, t_DJIT and t_RJIT specifications are Guaranteed by Design using statistical analysis.
Note 6: t_RJIT specification is the rms jitter measurement of the serializer output when the device is transmitting SYNC pattern.
Note 7: t_DJIT specification is measured with the serializer output transmitting PRBS pattern from the internal BIST mode. It is a measurement of the center
distribution of 0V (differential) crossing in comparsion with the ideal bit position. See Figure 9
AC Timing Diagrams and Test Circuits
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FIGURE 1. ’Worst Case Icc Test Pattern
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