DS92LV8028 Datasheet, PDF (15/16 Pages) National Semiconductor (TI) – 8 Channel 10:1 Serializer

Pin Descriptions (Continued)
Pin Number
G5, G8, G9, H5, H6, H8, H9,
J5, J6, J7, J9, J10
C1, D1
D2, D3
Name
NC (1:12)
PGND
PVDD
N1, N2, N13, M1, M2, M12,
PWDN (0:7)
P13, P14
J8, K5, K7, K8, K9, L1, L2,
SYNC (0:7)
N12
C13 TCK
B14
TDI
C14 TDO
A14 TMS
C12 TRSTN
F14 TCLK
Type
3.3 V
CMOS
I
3.3 V
CMOS
I
3.3 V
CMOS
I
Description
No connect.
PLL ground.
PLL power supply.
Individual Powerdown. PWDN (0:7) driven low puts individual
serializer into TRI-STATE, low power ’sleep’ mode. Default at
Low.
SYNC pattern enable. When driven high for a mininum of 4
cycles, SYNC patterns will be transmitted on the Bus LVDS
serial output. The SYNC pattern sent by the serializer consists
of six ones and six zeros switching at the input clock rate.
SYNC pattern continues to be sent if SYNC continues at high.
Default at Low. See Functional Description.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
Transmit Clock. Input for 25MHz - 66 MHz (nominal) system
clock.
15
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