DS92LV8028 Datasheet, PDF (12/16 Pages) National Semiconductor (TI) – 8 Channel 10:1 Serializer

Application Information (Continued)
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. The PLL(s) require
clean power for the minimization of Jitter. A supply noise
frequency in the 300kHZ to 1MHz range can cause in-
creased output jitter. Certain power supplies may have
switching frequencies or high harmonic content in this range.
If this is the case, filtering of this noise spectrum may be
required. A notch filter response is best to provide a stable
VDD, suppression of the noise band, and good high-
frequency response (clock fundamental). This may be ac-
complished with a pie filter (CRC or CLC). The pie filter
should be located close to the PVDD power pin. Separate
power planes for the PVDD pins is typically not required.
AVDD = LVDS SECTION POWER SUPPLY
The AVDD pin supplies the LVDS portion of the circuit. The
DS92LV8028 has nine AVDD pins. Due to the nature of the
design, current draw is not excessive on these pins. A 0.1uF
Application Diagram
capacitor is sufficient for these pins. If space is available, a
0.01uF may be used in parallel with the 0.1uF capacitor for
additional high frequency filtering.
GROUNDs
The AGND pin should be connected to the signal common in
the cable for the return path of any common-mode current.
Most of the LVDS current will be odd-mode and return within
the interconnect pair. A small amount of current may be
even-mode due to coupled noise, and driver imbalances.
This current should return via a low impedance known path.
A solid ground plane is recommended for DVDD, PVDD and
AVDD. Using a split plane may have a potential problem of
ground loops, or difference in ground potential at various
ground pins of the device.
FIGURE 12. Typical Application Circuit
20027210
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