DS92LV010A Datasheet, PDF (8/10 Pages) National Semiconductor (TI) – Bus LVDS 3.3/5.0V Single Transceiver

Application Information (Continued)
• Bypass each BLVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-
layer ceramic (MLC) surface mount capacitors (0.1 µF,
and 0.01 µF in parallel should be used between each V_CC
and ground. The capacitors should be as close as pos-
sible to the V_CC pin.
• Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)
TABLE 1. Functional Table
MODE SELECTED
DRIVER MODE
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
DE
RE
H
H
L
L
L
H
H
L
TABLE 2. Transmitter Mode
INPUTS
DE
DI
H
L
H
H
H 2 > & > 0.8
L
X
OUTPUTS
DO+
DO−
L
H
H
L
X
X
Z
Z
L = Low state
H = High state
TABLE 3. Receiver Mode
INPUTS
RE
(RI+)-(RI−)
L
L (< −100 mV)
L
H (> +100 mV)
L
100 mV > & > −100 mV
H
X
X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Pin Name
DIN
DO±/RI±
R_OUT
RE
DE
GND
V_CC
Pin #
2
6, 7
3
5
1
4
8
TABLE 4. Device Pin Description
Input/Output
I
I/O
O
I
I
NA
NA
Description
TTL Driver Input
LVDS Driver Outputs/LVDS Receiver Inputs
TTL Receiver Output
Receiver Enable TTL Input (Active Low)
Driver Enable TTL Input (Active High)
Ground
Power Supply
OUTPUT
L
H
X
Z
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