DS92LV010A Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Bus LVDS 3.3/5.0V Single Transceiver

May 1998
DS92LV010A
Bus LVDS 3.3/5.0V Single Transceiver
General Description
The DS92LV010A is one in a series of transceivers designed
specifically for the high speed, low power proprietary bus
backplane interfaces. The device operates from a single
3.3V or 5.0V power supply and includes one differential line
driver and one receiver. To minimize bus loading the driver
outputs and receiver inputs are internally connected. The
logic interface provides maximum flexibility as 4 separate
lines are provided (DIN, DE, RE, and ROUT). The device
also features flow through which allows easy PCB routing for
short stubs between the bus pins and the connector. The
driver has 10 mA drive capability, allowing it to drive heavily
loaded backplanes, with impedance as low as 27 Ohms.
The driver translates between TTL levels (single-ended) to
Low Voltage Differential Signaling levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is ±100mV over a ±1V common
mode range and translates the low voltage differential levels
to standard (CMOS/TTL) levels.
Features
n Bus LVDS Signaling (BLVDS)
n Designed for Double Termination Applications
n Balanced Output Impedance
n Lite Bus Loading 5pF typical
n Glitch free power up/down (Driver disabled)
n 3.3V or 5.0V Operation
n ±1V Common Mode Range
n ±100mV Receiver Sensitivity
n High Signaling Rate Capability (above 100 Mbps)
n Low Power CMOS design
n Product offered in 8 lead SOIC package
n Industrial Temperature Range Operation
Connection Diagram
Block Diagram
DS100052-1
Order Number DS92LV010ATM
See NS Package Number M08A
DS100052-2
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© 1998 National Semiconductor Corporation DS100052
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