DS92LV010A Datasheet, PDF (7/10 Pages) National Semiconductor (TI) – Bus LVDS 3.3/5.0V Single Transceiver

Test Circuits and Timing Waveforms (Continued)
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
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FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
Typical Bus Application Configurations
Bi-Directional Half-Duplex Point-to-Point Applications
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Multi-Point Bus Applications
Application Information
There are a few common practices which should be implied
when designing PCB for BLVDS signaling. Recommended
practices are:
• Keep drivers and receivers as close to the (BLVDS port
side) connector as possible.
• Use at least 4 layer PCB board (BLVDS signals, ground,
power and TTL signals).
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