DS90CR218A_06 Datasheet, PDF (8/11 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos Ideal — Calculated Transmitter output pulse position
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7)
+ TPPOS variance (Tx dependent)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than 250 ps at 85MHz
Note 7: ISI is dependent on interconnect length; may be zero
10108020
FIGURE 9. Receiver LVDS Input Skew Margin
Applications Information
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
DS90CR218A Pin Descriptions — Channel Link Receiver
I/O No.
Description
I
3 Positive LVDS differential data inputs.
I
3 Negative LVDS differential data inputs.
O 21 TTL level data outputs.
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
I
1 TTL level input. When asserted (low input) the receiver outputs are low.
I
4 Power supply pins for TTL outputs.
I
5 Ground pins for TTL outputs.
I
1 Power supply for PLL.
1
2 Ground pin for PLL.
I
1 Power supply pin for LVDS inputs.
I
3 Ground pins for LVDS inputs.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For
example, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less
critical. For higher speed/long distance applications the me-
dia’s performance becomes more critical. Certain cable con-
structions provide tighter skew (matched electrical length
between the conductors and pairs). Twin-coax for example,
has been demonstrated at distances as great as 5 meters
and with the maximum data transfer of 1.785 Gbit/s. Addi-
tional applications information can be found in the following
National Interface Application Notes:
AN = ####
AN-1041
AN-1108
AN-1109
AN-806
AN-905
AN-916
Topic
Introduction to Channel Link
Channel Link PCB and Interconnect
Design-In Guidelines
Multi-Drop Channel-Link Operation
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
Cable Information
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