DS90CR218A_06 Datasheet, PDF (1/11 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

October 2006
DS90CR218A
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 12 MHz to 85 MHz
General Description
The DS90CR218A receiver deserializes three input LVDS
data streams into 21 bits of CMOS/TTL output data. When
operating at the maximum input clock rate of 85 Mhz, the
LVDS data is received at 595 Mbps per data channel for a
total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR218A is
an ideal means to solve EMI and cable size problems asso-
ciated with wide, high-speed TTL interfaces.
Features
n 12 to 85 MHz shift clock support
n 50% duty cycle on receiver output clock
n Low power consumption
n ±1V common-mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.785 Gbps throughput
n Up to 223 Mbytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagram
DS90CR218A
Connection Diagrams
Order Number DS90CR218AMTD
See NS Package Number MTD48
10108027
DS90CR218A
10108022
© 2006 National Semiconductor Corporation DS101080
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